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About the Role

We are seeking a Senior Technologist to lead the design and implementation of an ultra-low-latency electronic trading platform targeting microsecond and sub-microsecond latencies. This role requires deep expertise across multiple domains: protocol design, distributed systems, market data infrastructure, hardware acceleration, and operational resilience. The successful candidate will own the technical strategy, establish engineering standards, and ensure the stack meets aggressive latency targets while maintaining deterministic failover capabilities and production reliability.

Responsibilities

Design the foundational messaging layer, evaluating trade-offs between FIX and Simple Binary Encoding.
Architect FPGA-based acceleration for latency-critical paths, including market data parsing, order matching, risk checks, and order routing.
Define which components warrant FPGA implementation based on latency budgets, throughput requirements, and cost trade-offs.
Work with vendors such as Exegy, Redline, et al. and establish FPGA trading components.
Architect the system to bypass the kernel network stack entirely using technologies like DPDK or Open Onload.
Design interrupt handling, packet batching, and memory management to minimize context switches and system call overhead.
Establish CPU affinity and isolation strategies, including CPU pinning, isolcpus kernel parameter configuration, and NUMA optimization.
Architect the sequencer component that creates deterministic, replayable event streams with minimal latency overhead.
Design the sequencer's durability model, sequence numbering schemes, and handling of clock skew, network partitions, and replica synchronization.
Ensure the sequenced stream enables stateless recovery of replicas without introducing bottlenecks.
Design the market data ingestion layer targeting microsecond-scale processing.
Evaluate direct feeds, FPGA-based feed parsing, and kernel-bypass software processing for market data ingestion.
Establish data normalization strategies that minimize CPU overhead and latency.
Lead design of the Direct Market Access engine targeting sub-ten-microsecond order processing.
Handle concurrent market data consumption, atomic order state management, and consistent failover with minimal latency impact.
Define the order lifecycle state machine and handle edge cases.
Ensure the DMA engine can replay from the sequenced stream deterministically.
Design the abstraction layer that normalizes venue protocols, enabling the system to support multiple markets without sacrificing latency.
Define the venue adapter pattern with minimal overhead and establish common order entry contracts.
Ensure venue-specific idiosyncrasies are encapsulated.
Design the risk check framework targeting sub-microsecond enforcement.
Define enforcement models and evaluate which checks warrant FPGA acceleration versus software optimization.
Establish how risk checks interact with the order flow and define bypass procedures for emergency scenarios.
Ensure risk logic is testable and auditable.
Architect the replica management strategy for ultra-low-latency systems.
Define consistency models appropriate for trading and recovery time objectives.
Design the network topology with latency as a primary constraint.
Evaluate placement in colocation facilities and minimize network hops.
Design the monitoring infrastructure that observes the system without introducing latency or jitter.
Establish nanosecond-precision timing for latency measurements and define alert thresholds.
Identify and implement ultra-low-latency optimizations: kernel bypass, CPU pinning, lock-free data structures, memory layout optimization, NUMA awareness, cache line alignment, SIMD optimization, branch prediction tuning, and custom CPU instruction usage.

Requirements

Ultra-Low-Latency Systems Engineering
Distributed Systems & Deterministic Computing
Financial Markets & High-Frequency Trading
Message Protocol & Serialization Design
Kernel-Level Systems Programming & OS Optimization
Performance Engineering & Profiling at Scale
Systems Programming & Production Operations

Skills

Application Development
Application Maintenance
Applications Architecture
Commercial Acumen
Enterprise Application Delivery
Information Technology Management
Information Technology Trends
Programming Languages
System Applications

Location

New York, United States of America

Work Type

Full time
Salaried

Experience Level

Senior

Salary/Compensations

$210,000 - $275,000

Benefits

Discretionary bonus
401(K) Program with company-matching contributions
Health, Dental, Vision, Life and Disability Insurance
Paid Time-Off Plan

About the Company

At RBC, we are guided by living shared values of Client First, Integrity, Collaboration, Respect and Excellence and winning together as One RBC.
We believe an inclusive workplace that has diverse perspectives is core to our continued growth as one of the largest and most successful banks in the world.
Maintaining a workplace where our employees feel supported to perform at their best, effectively collaborate, drive innovation, and grow professionally helps to bring our Purpose to life and create value for our clients and communities.
RBC strives to deliver this through policies and programs intended to foster a workplace based on respect, belonging and opportunity for all.