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About the Role

We are seeking a Senior Hardware Architect to focus on Reliability, Availability, and Serviceability (RAS) for Tegra System-on-Chips (SoCs). This role involves defining resilient computing platforms for datacenters, autonomous vehicles, edge systems, and other high-reliability applications. You will define, drive, and deliver RAS hardware architecture across advanced CPUs and SoCs through the entire product development lifecycle.

Responsibilities

Define and drive SoC-level RAS hardware architecture across CPUs, interconnects, memory systems, IOs, safety islands, firmware interfaces, and platform-level components.
Own RAS features from concept through architecture specification, micro-architecture alignment, RTL implementation support, design verification, silicon validation, debug, and production readiness.
Develop architectural requirements for fault detection, correction, containment, isolation, telemetry, error reporting, recovery, graceful degradation, serviceability, and diagnostic observability.
Work closely with design, verification, validation, firmware, software, and platform teams to ensure RAS features are implementable, verifiable, debuggable, and aligned with system-level requirements.
Understand the broader SoC architecture and identify how RAS mechanisms interact with performance, power, reset flows, clocks, memory hierarchy, interconnect behavior, firmware-visible controls, and platform software.
Create hardware specifications, architectural requirements, error-handling flows, design guidance, test plans, and architectural models in SystemC, C/C++, Python, or other relevant modeling environments.
Plan and review verification and validation strategies for RAS mechanisms, including error injection, recovery validation, coverage analysis, resiliency modeling, and architecture reviews.
Assist in failure analysis and silicon debug for lab, post-silicon, production, and field findings; develop diagnostic screens and localization methods for latent, intermittent, and environment-sensitive failures.
Apply RAS architecture principles to high-reliability deployment environments, including space-aware and radiation-aware use cases.
Follow industry standards and research related to RAS, functional safety, semiconductor reliability, debuggability, verification, validation, and silicon testing.
Patent novel hardware architecture techniques that improve system resiliency, observability, serviceability, and recovery.

Requirements

MS or PhD degree in computer engineering, electrical engineering, or equivalent experience.
At least 8+ years of SoC architecture, design, verification, reliability, silicon validation, or related hardware development experience.
Strong understanding of Reliability, Availability, and Serviceability (RAS) in the SoC context, including fault detection, correction, containment, telemetry, recovery, degradation modes, debug visibility, and serviceability mechanisms.
Experience defining and driving hardware architecture features through the full development lifecycle, including architecture definition, design implementation, verification planning, validation, debug, and production readiness.
Strong understanding of overall SoC architecture and the ability to reason across micro-architecture, full-chip integration, firmware interfaces, software-visible behavior, platform flows, and customer use cases.
Meaningful industry expertise in one or more SoC architecture areas such as RAS, safety, debug, clocks, resets, interconnects, memory controllers, IO technologies, platform integration, firmware-visible error handling, or diagnostic infrastructure.
Hands-on experience with design verification, silicon validation, fault injection, coverage analysis, resiliency modeling, diagnostic development, or reliability validation methodology.
Familiarity with radiation effects, space operation, or other high-reliability deployment environments is strongly valued, including understanding how hardware architecture can mitigate single-event effects and related reliability risks.
Excellent analytical, written, and verbal interpersonal skills with the ability to work effectively across architecture, design, verification, firmware, software, validation, and customer-facing teams.

Skills

SystemC
C/C++
Python
Reliability, Availability, and Serviceability (RAS)
Fault detection
Fault correction
Fault containment
Telemetry
Error reporting
Recovery
Graceful degradation
Serviceability
Diagnostic observability
SoC architecture
Micro-architecture
Full-chip integration
Firmware interfaces
Software-visible behavior
Platform flows
Design verification
Silicon validation
Fault injection
Coverage analysis
Resiliency modeling
Diagnostic development
Reliability validation
Radiation effects
Space operation
ECC
Parity
Redundancy
Replay
Checkpoint/restart
Scrubbing
Isolation
Containment
Error logging
Design for Debug
Design for Test
Design for Reliability
Silicon observability

Location

Remote

Work Type

Full-time

Experience Level

Senior
8+ years

Education Level

MS or PhD degree in computer engineering, electrical engineering, or equivalent experience

Salary/Compensations

184,000 USD – 287,500 USD for Level 4
224,000 USD – 356,500 USD for Level 5

Benefits

Equity
Benefits

About the Company

NVIDIA is widely considered to be one of the technology world’s most desirable employers.
We have some of the most forward-thinking and hardworking people in the world working for us.
NVIDIA uses AI tools in its recruiting processes.

Equal Opportunity

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer.
As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.