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About the Role
Partner with domain experts, EDA vendors, and product design teams to develop and deliver industry-leading memory technology collaterals. Drive innovations for next-generation high-performance, high-density, low-power embedded memory designs on Intel's advanced CMOS process technologies.
Responsibilities
- Define, develop, and optimize advanced memory bitcells, array architectures, and peripheral circuits.
- Lead memory pathfinding and optimize power, performance, and area (PPA) through design-technology co-optimization (DTCO) and product design enablement.
- Develop and validate memory libraries for PDK enablement across Intel's advanced process technologies.
- Design memory arrays and IP, develop innovative memory circuits, and execute and validate test chips.
Requirements
- BA degree with 3 years of experience or Master's degree in Electrical Engineering, Computer Engineering, or a related STEM field with 2+ years of experience OR a PhD with no experience.
- Experience in customer circuit design, simulation, layout design and verification.
- Hands-on experience with relevant industry EDA tools and flows for digital and/or analog design and verification, such as Cadence Virtuoso, Synopsys StarRC, and Synopsys HSPICE.
- Experience in memory bitcell and circuit design.
- Experience with advanced CMOS process technologies and device physics.
- Experience evaluating and balancing power, performance, and area trade-offs.
- Experience designing, characterizing, and verifying custom memory circuits, such as SRAM, register files, and ROM.
- Experience optimizing the physical design of custom circuits.
Skills
- Circuit design
- Simulation
- Layout design
- Verification
- EDA tools
- Digital design
- Analog design
- Memory bitcell design
- Memory circuit design
- CMOS process technologies
- Device physics
- Power, performance, and area (PPA) trade-offs
- SRAM
- Register files
- ROM
- Physical design optimization
Location
- US, Oregon, Hillsboro
- US, California, Santa Clara
- US, Texas, Austin
Work Type
- Hybrid
- College Grad
- Shift 1
Experience Level
- 3 years of experience (with BA)
- 2+ years of experience (with Master's)
- No experience (with PhD)
Education Level
- BA degree
- Master's degree in Electrical Engineering, Computer Engineering, or a related STEM field
- PhD
Salary/Compensations
- $105,650.00-200,340.00 USD
Benefits
- Competitive pay
- Stock bonuses
- Health benefits
- Retirement benefits
- Vacation benefits
About the Company
- The Advanced Design (AD) team is part of Intel’s larger Design Technology Platform (DTP) Organization, focused on pathfinding and development of advanced memory technology.
- These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology.
- DTP is one of the key pillars enabling Intel to deliver winning products in the marketplace.
- Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.
- We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment.
Equal Opportunity
- All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.