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About the Role
Work with all fields (vertical product models) with a critical impact in getting impactful products to millions of customers quickly. Work closely with Architecture to understand the performance goals of the design. Correlate RTL performance against model performance. Perform deep performance analysis in the design and report findings. Identify performance bottlenecks in design and coordinate with the Architecture team to improve performance. Define performance statistics to help with performance debugging and standard methodologies to enhance performance correlation effort. Utilize strong interpersonal skills, work independently, and lead work to align with the project goals, plus support multi-functional engineering efforts. Work with Architecture, Modeling, Micro-Architecture, Design, and Verification teams for performance test plan definition. Drive the definition of the testing methodology for executing the test plan. Develop testbench infrastructure for monitoring, checking and covering on-chip activity in SystemVerilog, and C++. Architect and implement data analysis and visualization methodologies of simulation performance data. Design and Performance Model. Review results and analysis of performance validation work with the cross-functional audience.
Responsibilities
- Correlate RTL performance against model performance.
- Perform deep performance analysis in the design and report findings.
- Identify performance bottlenecks in design and coordinate with the Architecture team to improve performance.
- Define performance statistics to help with performance debugging and standard methodologies to enhance performance correlation effort.
- Utilize strong interpersonal skills, work independently, and lead work to align with the project goals, plus support multi-functional engineering efforts.
- Work with Architecture, Modeling, Micro-Architecture, Design, and Verification teams for performance test plan definition.
- Drive the definition of the testing methodology for executing the test plan.
- Develop testbench infrastructure for monitoring, checking and covering on-chip activity in SystemVerilog, and C++.
- Architect and implement data analysis and visualization methodologies of simulation performance data.
- Design and Performance Model.
- Review results and analysis of performance validation work with the cross-functional audience.
Requirements
- Experience in Computer Architecture, including Cache Coherency, Cache Hierarchy Fundamentals, Fabric Interconnect fundamentals to help debug performance bottlenecks
- Experience in Data Structures and Algorithms, including using python, C++ and System Verilog to work on multi-language codebases.
- Experience in Object Oriented Programming, including using python, C++ and System Verilog to work on multi-language codebases.
- Using waveform viewers to debug performance bottlenecks in hardware, including developing System Verilog monitors to automate performance stat collection.
- Using C and C++, including updating and reviewing software model used to represent the hardware.
- Scripting in Python and Perl experience, including using scripting in Python and Perl to analyze and provide visual representation of performance data.
- Experience in design verification to help develop robust test plans.
Skills
- SystemVerilog
- C++
- Python
- Perl
- Cache Coherency
- Cache Hierarchy Fundamentals
- Fabric Interconnect fundamentals
- Data Structures
- Algorithms
- Object Oriented Programming
- waveform viewers
- C
Location
- Austin, Texas
Work Type
- 40 hours/week
Experience Level
- 2 years of experience
Education Level
- Master’s Degree or foreign equivalent in Electrical Engineering, Computer Engineering, or related field
About the Company
- Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.