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About the Role

Design complex custom layout for digital circuits in deep SubMicron CMOS technologies. Work with Layout lead and circuit designers to review and analyze floorplans of complex circuits. Responsible to run a complete set of layout design verification tools available and clean up megacells to match engineering specifications. Work with Layout lead and circuit design team to plan, schedule work and negotiate layout tradeoffs as needed. Interpret LVS, DRC and ERC report to find the fastest way to complete layouts. Utilize advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits. Utilize advanced layout techniques to come up with best-in-class PPA for critical designs. Work with design lead to review EMIR simulations and apply necessary fixes to achieve robust power delivery. Utilize automated P&R tools to speed up the layout execution of digital designs. 40 hours/week.

Responsibilities

Design complex custom layout for digital circuits in deep SubMicron CMOS technologies.
Review and analyze floorplans of complex circuits with the Layout lead and circuit designers.
Run layout design verification tools and clean up megacells to match engineering specifications.
Plan, schedule work, and negotiate layout tradeoffs with the Layout lead and circuit design team.
Interpret LVS, DRC, and ERC reports to complete layouts efficiently.
Apply advanced CAD tools and mask design knowledge for layout corrections and robust physical design.
Utilize advanced layout techniques to achieve best-in-class PPA for critical designs.
Review EMIR simulations and apply fixes for robust power delivery with the design lead.
Use automated P&R tools to accelerate layout execution for digital designs.

Requirements

Using layout floor-planning, standard cell planning and hierarchical layout assembly to generate best PPA (power, performance and area) layouts.
Resolving issues with RC delay, electromigration, self-heating and cross capacitance.
Recognizing failure prone layout structures and working with designers for the best approach to problems including shielding critical signals, analyzing DFM yields, and LOD effects.
Creating layouts with a robust PG grid using IR simulations tools.
Collaborating and communicating effectively with multi-functional teams to understand engineering specifications and ensure on-time deliverables.
Interpreting CALIBRE DRC, ERC, LVS, and DFM reports to finish layout(s).
Using CADENCE virtuoso layout design tools to draw layouts and increase productivity.

Skills

Layout floor-planning
Standard cell planning
Hierarchical layout assembly
RC delay resolution
Electromigration resolution
Self-heating resolution
Cross capacitance resolution
DFM yield analysis
LOD effects analysis
IR simulations
CALIBRE DRC
CALIBRE ERC
CALIBRE LVS
CALIBRE DFM
CADENCE virtuoso layout design tools
Automated P&R tools

Location

Austin, Texas

Work Type

40 hours/week

Experience Level

2 years of experience

Education Level

Bachelor's degree or foreign equivalent in Electrical Engineering or related field

About the Company

Apple is a place where extraordinary people gather to do their lives best work.
Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without.
It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.