Design Verification Engineer at Apple | Austin, TX, US | Rezi

Design Verification Engineer at Apple

Design Verification Engineer

Apple · Austin, TX, US

2 days ago

Design Verification Engineer

Apple · Austin, TX, US

2 days ago
Resume preview

Impress employers and recruiters.
Choose from hundreds of resume examples.

Target Resume Now
Resume preview

Tailor your resume to this Design Verification Engineer role.

Rezi rewrites your resume against Apple's job description. Free.

Resume score gauge reading 58 out of 100

Don't guess if your resume is good enough.

See how it scores against the Design Verification Engineer posting at Apple — free, in seconds.

About the Role

Join our team to verify innovative, high-throughput cellular baseband modems and transceiver link controllers that power communication for millions of users worldwide. As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems. Working on innovative baseband modems and RF link controllers for Apple's SOCs, you'll craft highly reusable UVM verification environments that set the standard for quality and efficiency. You'll develop comprehensive coverage-driven and directed test cases that thoroughly validate complex IP and subsystem designs, working closely with multi-functional teams throughout the process. In this role, you'll drive methodology innovation by deploying sophisticated tools and techniques that elevate verification practices and ensure tape-out readiness. Collaborating with product development teams across Apple, you'll help deliver cellular systems that redefine industry capabilities and enhance customer experiences globally. This position offers exceptional opportunities to deepen your expertise across cellular protocols, complex IP and subsystem architectures, advanced fabric protocols, and sophisticated debug methodologies. You'll gain experience with best-in-class design verification practices, co-verification techniques with models and firmware, and industry-standard low-power architectures.

Responsibilities

  • Craft highly reusable UVM verification environments.
  • Develop comprehensive coverage-driven and directed test cases.
  • Validate complex IP and subsystem designs.
  • Work closely with multi-functional teams.
  • Drive methodology innovation by deploying sophisticated tools and techniques.
  • Elevate verification practices and ensure tape-out readiness.
  • Collaborate with product development teams across Apple.
  • Deliver cellular systems that redefine industry capabilities and enhance customer experiences globally.
  • Deepen expertise across cellular protocols, complex IP and subsystem architectures, advanced fabric protocols, and sophisticated debug methodologies.
  • Gain experience with best-in-class design verification practices, co-verification techniques with models and firmware, and industry-standard low-power architectures.

Requirements

  • BS and a minimum of 10 years relevant industry experience.
  • Strong knowledge of System Verilog and UVM.
  • Skilled in System C, C/C++, Python/perl.
  • Highly proficient in developing and establishing DV Methodologies.
  • Experience in using LLMs and MCPs.
  • Experience with developing Python-based automation solutions.
  • Experience with constraint random testing, SVA, Coverage driven verification.
  • Strong test planning and problem-solving skills.
  • Master of Science degree in Electrical Engineering/Computer Science.
  • Experience in C/C++ modeling for design verification.
  • Knowledge of 4G/5G cellular physical layer operation (3GPP).
  • Experience with verification of embedded processor cores.
  • Hands-on verification experience of Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
  • Experience using LLMs to improve efficiency and quality of verification.
  • Understanding of prompt engineering and LLM workflow optimization.

Skills

  • System Verilog
  • UVM
  • System C
  • C/C++
  • Python/perl
  • DV Methodologies
  • LLMs
  • MCPs
  • Python-based automation
  • Constraint random testing
  • SVA
  • Coverage driven verification
  • Test planning
  • Problem-solving
  • C/C++ modeling
  • 4G/5G cellular physical layer operation (3GPP)
  • Embedded processor core verification
  • Bus Fabric verification
  • NOC verification
  • AHB verification
  • AXI verification
  • Prompt engineering
  • LLM workflow optimization

Experience Level

  • 10 years relevant industry experience

Education Level

  • BS
  • Master of Science degree in Electrical Engineering/Computer Science

About the Company

  • Apple is where individual imaginations gather together, committing to the values that lead to great work.
  • Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger.
  • That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better.
  • It’s the diversity of our people and their thinking that inspires the innovation that runs through everything we do.
  • When we bring everybody in, we can do the best work of our lives.
  • Here, you’ll do more than join something — you’ll add something.