Impress employers and recruiters.
Choose from hundreds of resume examples.

Target Resume Now

Tailor your resume to this Design Engineering Architect – Systems and Interfaces role.

Rezi rewrites your resume against Cadence Design Systems's job description. Free.

Resume score gauge reading 58 out of 100

Don't guess if your resume is good enough.

See how it scores against the Design Engineering Architect – Systems and Interfaces posting at Cadence Design Systems — free, in seconds.

About the Role

Serve as a senior technical leader enabling the successful integration and adoption of Cadence interface IP in customer SoCs. Work closely with sales, marketing, development engineering, and customer support teams to contribute to product definition, develop technical content, and drive pre-sales and post-sales engagements.

Responsibilities

Serve as the technical authority for Cadence interface controllers and system-level IP integration in customer engagements.
Lead resolution of critical customer issues and escalations, coordinating with development engineering, sales, marketing, and customer support teams on pre-sales and post-sales engagements.
Develop reference designs, technical collateral, and application notes for IP integration, SoC design, and verification.
Develop and deliver training for customers and field application engineers.
Provide advanced technical guidance to customers, support teams, and field application engineers on IP integration, configuration, and system-level deployment.
Lead product evaluations and release-readiness reviews, identifying integration risks, usability gaps, and advanced customer use cases.
Analyze and propose enhancements to our products and documentation based on customer needs and use cases.

Requirements

Demonstrated expertise in the RTL design, verification, and debug of high-speed interface protocols such as PCIe, UCIe, and Ethernet.
Experience integrating IP into complex SoCs, with a strong understanding of system architecture, interfaces, and on-chip interconnects.
Experience with AMBA protocols, including ACE, CHI, AXI, and APB.
Proficient in writing and debugging RTL (Verilog, SystemVerilog).
Experience with end-to-end SoC implementation flows, including RTL synthesis, design constraints, DFT, CDC, and static timing analysis.
Demonstrated ability to analyze complex hardware and system problems, identify root causes, and drive cross-functional teams to resolution.
Strong written and verbal communication skills.
Ability to travel up to 10% of the time, including internationally.

Skills

PCIe
UCIe
Ethernet
AMBA protocols (ACE, CHI, AXI, APB)
RTL design
RTL verification
RTL debug
Verilog
SystemVerilog
SoC implementation flows
RTL synthesis
Design constraints
DFT
CDC
Static timing analysis

Location

San Jose

Work Type

Full-time

Experience Level

12+ years (BS in EE/CS)
8+ years (MS in EE/CS)

Education Level

BS in EE/CS
MS in EE/CS

Salary/Compensations

$185,500 to $344,500

Benefits

Incentive compensation: bonus, equity
Competitive On Target Earnings (OTE) incentive compensation structure for sales positions
Paid vacation
Paid holidays
401(k) plan with employer match
Employee stock purchase plan
Variety of medical, dental and vision plan options

About the Company

Cadence hires and develops leaders and innovators who want to make an impact on the world of technology.
The Cadence Silicon Solutions Group (SSG) develops and licenses IP for SoC and ASIC designs, including high-performance DSPs, CPUs, interface IP, DDR controllers, hardware accelerators, and subsystems.
These technologies enable applications such as machine learning, edge AI, radar, audio, speech, and vision.
Leading semiconductor companies use Cadence IP in billions of chips shipped annually.
We’re doing work that matters. Help us solve what others can’t.