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About the Role

Designs the physical silicon layout for high-frequency or high-speed mixed-signal circuits, including SerDes, ADCs, DACs, PLLs, and high-speed blocks.

Responsibilities

Create block-level and chip-top-level floor plans.
Manage hierarchical block integration.
Handle micro-bump or package-aware co-design.
Address layout-dependent effects (LOD, WPE, LDE).
Implement device matching, common-centroid structures, guard rings, and isolation or shielding (coaxial, differential, ground shields).
Ensure closure on DRC, LVS, ERC, and antenna rules.
Perform EM/IR reliability and ESD protection verification.

Requirements

7+ years of relevant experience.
Experience with TSMC 4NM is required.
Experience at lower nodes (N3, N5) is critical.

Skills

Custom IC layout
Deep sub-micron or advanced CMOS/FinFET nodes
TSMC N3
TSMC N5
TSMC N7
SerDes
ADCs
DACs
PLLs
High-speed blocks
Floor planning
Hierarchical block integration
Micro-bump co-design
Package-aware co-design
Layout-dependent effects (LOD, WPE, LDE)
Device matching
Common-centroid structures
Guard rings
Isolation
Shielding
DRC
LVS
ERC
Antenna rules
EM/IR reliability
ESD protection

Location

Austin, TX

Work Type

Remote

Experience Level

7+ years

About the Company

Client: Arrow Electronics