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About the Role
Meta is developing custom silicon for AR glasses, focusing on computer vision, machine learning, imaging, and sensing. We are seeking a Design Verification (DV) lead to manage the verification of complex computer vision and imaging accelerator IP and subsystems. This role involves defining verification strategies and building scalable DV infrastructure.
Responsibilities
- Shape architecture and microarchitecture decisions with cross-functional teams to ensure designs are verification-friendly.
- Manage schedules and sign-off criteria with TPMs.
- Own DV for complex IPs or subsystems from planning through coverage closure and sign-off.
- Define verification strategies including simulation, formal, assertions, emulation, FPGA prototyping, and power-aware verification.
- Design reusable testbench architectures, verification IP, and libraries for cross-chip and cross-generation use.
- Drive regression management, automated triage, coverage analytics, and compute-efficient runs.
- Identify and address verification quality and productivity gaps, leading initiatives for improvement.
- Drive DV methodology improvements, including AI-assisted approaches.
- Root-cause failures to RTL, reference model, or FW/SW and propose solutions.
Requirements
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
- 8+ years of hands-on verification experience with SystemVerilog, UVM, and C/C++ at IP, subsystem, and SoC levels.
- Experience leading DV for complex IP or SoC through tape-out, including sign-off ownership.
- Experience defining and executing verification plans, coverage strategies, and closure metrics.
- Experience building UVM verification environments and reusable verification components from scratch.
- Deep experience in at least one of: formal verification, SystemVerilog Assertions (SVA), emulation/FPGA prototyping, or low-power (UPF) verification.
- Strong scripting skills (Python, TCL, Perl, Shell) for building verification tools and flows.
- Experience leading and mentoring engineers and coordinating cross-team work.
Skills
- SystemVerilog
- UVM
- C/C++
- Formal verification
- SystemVerilog Assertions (SVA)
- Emulation
- FPGA prototyping
- Low-power verification (UPF)
- Python
- TCL
- Perl
- Shell scripting
Location
- Remote
Work Type
- Full-time
Experience Level
- 8+ years
- Lead
Education Level
- Bachelor's degree
- Master's degree
- PhD
Salary/Compensations
- $178,000/year to $250,000/year
Benefits
- Bonus
- Equity
About the Company
- Meta is building custom silicon for AR glasses, focusing on computer vision, machine learning, imaging, and sensing.