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About the Role
Join Apple and contribute to the development of groundbreaking products. This role offers the opportunity to craft upcoming products that will delight millions of customers and transform hardware technology. You will be responsible for leading-edge IP development and coordinating with multiple SOC teams, executing design and integration tasks for high-quality IP deliverables.
Responsibilities
- Full chip and block level timing closure ownership throughout the entire project.
- Develop and maintain methodology and flows related to timing verification and closure.
- Generation of block and full chip timing constraints.
- Work closely with various multi-functional teams on resolving complex timing issues for major building blocks of complex SoCs.
Requirements
- Bachelors Degree + 3 Years of Experience.
- Strong fundamentals in the area of Digital design
- Self-starter and highly motivated
- Ability to communicate optimally across all internal groups
Skills
- Proficient in scripting languages (TCL and Perl)
- Familiarity with ASIC design timing concepts
- Exposure in STA tools (Primetime) is a plus
- Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks
- Familiarity in Constraint analysis and debug, using industry standard tools such as Synopsys GCA (Galaxy Constraint Analyzer) is desirable but not required
- Knowledge of timing corners/modes, process variations and signal integrity related issues is a plus
Location
- Apple
Work Type
- Full-time
Experience Level
- 3+ Years of Experience
Education Level
- Bachelors Degree
About the Company
- Apple is a company where new ideas become extraordinary products, services, and customer experiences.
- We are driven by passion and dedication, reinventing entire industries with our hardware products.
- Our commitment to innovation extends to our practices, strengthening our dedication to leave the world better than we found it.