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About the Role
Join our Digital Design Engineering group to transform imaginative ideas into reality. You will design state-of-the-art ASICs and create extraordinary custom digital macros and libraries using the latest technology nodes. This role offers endless learning opportunities within a fast-paced environment, collaborating with integration, CAD, circuit, and technology engineering teams.
Responsibilities
- Design complex custom layout for digital circuits in deep SubMicron CMOS technologies.
- Review and analyze floorplans and complex circuits with circuit designers.
- Run a complete set of layout design verification tools for megacells.
- Plan and schedule work with the circuit design team, negotiating layout tradeoffs.
- Interpret LVS, DRC, and ERC reports to efficiently complete layouts.
- Exceed engineering specifications and expectations.
- Utilize advanced CAD tools and mask design knowledge for layout corrections and robust physical design representation of circuits.
Requirements
- Minimum of a bachelor's degree in a related field.
- Experience in custom layout design of deep SubMicron CMOS circuits.
- High-level proficiency in layout floorplanning, standard cell planning, and hierarchical layout assembly.
- Good understanding of RC delay, electromigration, self-heating, and cross-capacitance issues.
- Ability to recognize failure-prone layout structures and collaborate with designers on problem-solving.
- Excellent communication skills and ability to work with multi-functional teams.
- Proficiency in interpreting CALIBRE DRC, ERC, LVS, etc. reports.
- Knowledge of MENTOR GRAPHICS or CADENCE layout tools.
Skills
- Custom layout design
- Deep SubMicron CMOS circuits
- Layout floorplanning
- Standard cell planning
- Hierarchical layout assembly
- RC delay analysis
- Electromigration analysis
- Self-heating analysis
- Cross-capacitance analysis
- CALIBRE DRC
- CALIBRE ERC
- CALIBRE LVS
- MENTOR GRAPHICS tools
- CADENCE layout tools
- CSH scripting
- PERL scripting
- SKILL scripting
- Layout automation
- Memory compiler development
- Low noise datapath design
- Low power datapath design
- Memory layout structures
Location
- Onsite
Work Type
- Full-time
Experience Level
- Custom layout design experience
- Experience in deep SubMicron CMOS circuits
- Experience with layout automation (plus)
- Experience in memory compiler development (plus)
- Experience designing low noise, low power datapaths or Memory layout structures
Education Level
- Bachelor's degree in related field
About the Company
- Apple's custom layout team is responsible for designing state-of-the-art ASICs.
- We are an exciting silicon design group responsible for designing state-of-the-art ASICs.