RTL-to-GDS implementation, Senior Principal Solutions Engineer
Cadence Design Systems · Austin, TX, US
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About the Role
Support the adoption of Cadence Products to help Chip Designer Customers achieve superior performance for their Design PPA Goals. Gain expertise in specialization tools, broadening focus from product emphasis to methodology, Full Flow Implementation Training, and leveraging success. Opportunity to get involved in competitive benchmarking on complex blocks including CPUs, GPUs and DSP cores.
Responsibilities
- Support the adoption of Cadence Products
- Achieve superior performance for Design PPA Goals
- Articulate design methodologies involving Cadence tools
- Gain expertise in additional or specialization tools
- Broaden focus from product emphasis to methodology
- Undertake Full Flow Implementation Training
- Learn to leverage success
- Own block implementation, top level implementation, and Signoff focused efforts
- Engage in RTL to GDSII delivery of projects
- Get involved in competitive benchmarking on complex blocks including CPUs, GPUs and DSP cores
- Manage strategic customer evaluations/benchmarks on Cadence's front-end solutions
- Establish technology differentiation and assert Cadence competitive advantages
- Multiplex several issues and set priorities
- Exploit new technologies
Requirements
- 7+ years experience and strong technical knowledge of company products
- ASIC design experience using industry-standard hardware description languages (Verilog)
- Deep Cadence or Synopsys place and route tool knowledge
- Physical Synthesis, PnR, CTS, Static Timing Analysis experience and knowledge are required
- Innovate with Low Power and Multi-Voltage Design Techniques working with leading edge Wireless and Mobile Customers
- Support RTL-to-GDS implementation flows using Encounter Digitial Implementation Platform
- Experience supporting tapeouts
- Experience with multivoltage design implementation and clock tree debugging is desirable
Skills
- Synthesis (logical and physical)
- Place and Route
- STA / SDC
- Verilog
- Physical Synthesis
- PnR
- CTS
- Static Timing Analysis
- Low Power Design Techniques
- Multi-Voltage Design Techniques
- Encounter Digitial Implementation Platform
- Elevator talk proficiency in the full Cadence tool portfolio
Experience Level
- Senior Principal
- Senior Level
- 7+ years experience
About the Company
- At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- We’re doing work that matters.
- Help us solve what others can’t.