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About the Role

As a Principal Design Engineer on the NAND datapath team, you will lead architecture and design of the internal datapath between the page buffer and IO. You will use AI daily to accelerate design, timing closure and verification, and help bring STA-based semi-custom methodology into a simulation-only flow.

Responsibilities

Define, design and verify internal datapath blocks to meet bandwidth, timing and power targets.
Architect and close wave-pipelined and flop-to-flop paths, including setup/hold, skew/jitter budgets, PVT delay tracking, and delay trims across PVT and aging.
Design dataline sense amps and precharge/latch sensing, covering offset, Monte Carlo/high-sigma margin, coupling and IR drop.
Design column repair, fuse/repair storage and redundancy muxing with no bandwidth or timing penalty; verify all repair configurations with test, PE and FW.
Use AI daily for RTL generation, scripting, and timing/waveform analysis; make specs and checklists AI-consumable and build agents that automate timing, Monte Carlo and repair-coverage checks.
Lead the move from SPICE-only closure to a semi-custom flow with characterized custom cells, SDC/STA sign-off, STA-to-SPICE correlation, and synthesis/APR/ECO flows.
Drive floorplan, bus routing and RC-aware delay matching with layout, and correlate post-layout timing.
Champion AI adoption and best practices, define interface specs with cross-functional teams, support silicon debug, and mentor engineers.

Requirements

BS/MS in EE or related field with 8+ years in memory datapath, SRAM or high-speed custom design.
Deep expertise in flop-to-flop and wave-pipelined timing closure (setup/hold, skew, min/max delay, PVT margin).
Experience in sense amp, dataline or SRAM read/write design, including Monte Carlo/high-sigma verification.
Proven collaboration with layout on floorplanning, extraction and post-layout timing correlation.
Daily hands-on AI use, with concrete examples of AI-based workflows (prompts, scripts or agents) that improved productivity or design outcomes.

Skills

NAND/DRAM/SRAM periphery experience: page buffer, column decoder, global data bus, or array-to-IO pipeline.
Memory repair and redundancy design, and its impact on yield, area, timing and test time.
Timing-adjustment techniques (delay trims, DLL/DCC, training) and aging effects (NBTI/HCI).
Building AI agents, LLM/RAG pipelines or ML models for IC design, verification or debug.
Advanced CMOS device physics, mismatch modeling (BSIM), and low-power techniques (clock/power gating, leakage).
Working knowledge of STA and semi-custom flows mixing custom and standard-cell logic.

Location

Remote

Work Type

Full-time

Experience Level

Principal

Education Level

BS/MS in EE or related field

About the Company

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all.
With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands.
Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

Equal Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.