Impress employers and recruiters.
Choose from hundreds of resume examples.

Target Resume Now

Tailor your resume to this CPU IP Design & Verification Engineer – RISC-V (2027 New College Graduate) role.

Rezi rewrites your resume against GlobalFoundries's job description. Free.

Resume score gauge reading 58 out of 100

Don't guess if your resume is good enough.

See how it scores against the CPU IP Design & Verification Engineer – RISC-V (2027 New College Graduate) posting at GlobalFoundries — free, in seconds.

About the Role

GlobalFoundries is seeking a New College Graduate CPU IP Design & Verification Engineer to join the MIPS CPU IP Engineering team. This role involves developing and verifying advanced RISC-V processor IP, providing hands-on experience in CPU microarchitecture, SystemVerilog RTL implementation, functional verification, power, performance, and area analysis, automation, and debug.

Responsibilities

Design and develop RISC-V CPU microarchitecture and SystemVerilog RTL design and development.
Contribute to CPU functions including instruction fetch and decode, execution, load/store, caches and memory interfaces, control and status registers, exceptions, and interrupts.
Develop verification tests, assertions, checkers, and functional coverage for CPU features.
Run CPU simulations and regressions and debug failures using logs, architectural traces, and waveforms.
Support functional and coverage closure through design and verification reviews.
Support CPU power, performance, and area analysis and optimization.
Develop Python, C/C++, or scripting-based automation to improve design, verification, regression, and debug productivity.
Collaborate across architecture, design, verification, performance, and implementation teams to deliver high-quality CPU IP.
Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

Requirements

Graduating with a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field from an accredited degree program.
Must have at least an overall 3.0 GPA and proven good academic standing.
English (Written & Verbal) language fluency.
Strong foundation in digital logic design and computer architecture.
Coursework, research, internship, or project experience with Verilog or SystemVerilog.
Understanding of CPU fundamentals including pipelines, instruction execution, loads/stores, caches, and memory hierarchy.
Programming or scripting experience with Python, C/C++, or similar languages.
Strong analytical, problem-solving, and debugging skills.

Skills

Python
C/C++
Verilog
SystemVerilog
RISC-V Instruction Set Architecture (ISA)
SystemVerilog/UVM
Assertions
Functional coverage
Constrained-random verification
CPU architecture
Microarchitecture
FPGA
ASIC
Processor-design
Caches
Memory subsystems
Privilege modes
Exceptions
Interrupts
Virtual memory
Simulation
Waveform debug
Git
Linux
Synthesis
Lint
Clock-domain crossing analysis
Formal verification
Timing analysis
Assembly-language programming
AI-assisted engineering tools

Location

Austin, Texas
Santa Clara, California

Work Type

Full-time

Experience Level

New College Graduate

Education Level

Bachelor’s Degree
Master’s Degree
PhD

Salary/Compensations

$86,000.00 - $170,000.00

About the Company

GlobalFoundries (GF) is a leading manufacturer of essential semiconductors, enabling AI at scale from the cloud to the physical world.
Through deep partnerships with customers, GF delivers differentiated, powerefficient and highperformance solutions for highgrowth markets.
GF is a trusted and holistic technology partner for customers around the world.
GF’s talented, global team remains focused every day on security, longevity and sustainability.

Equal Opportunity

GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential.
GlobalFoundries goal of excellence in business necessitates the attraction and retention of highly qualified people.
Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory.
All policies and processes which pertain to employees including recruitment, selection, training, utilization, promotion, compensation, benefits, extracurricular programs, and termination are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law.