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About the Role
As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers daily. This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs.
Responsibilities
- Establishing DV methodology
- Test-plan development
- Verification environment development including stimulus and checkers
- Test-writing
- Debug
- Coverage
- Sign-off for RTL freeze and tape-out
- Ensuring bug-free first silicon for part of the SoC / IP
- Develop detailed test and coverage plans based on the micro-architecture
- Developing verification methodology suitable for the IP
- Ensuring a scalable and portable environment
- Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage
- Develop verification plans for all features under your care
- Execute verification plans, including design bring-up, DV environment bring- up, regression enabling features, and debug of the test failures
- Develop block, IP and SoC level test-benches
- Track and report DV progress using a variety of metrics, including bugs and coverage
- Make use of LLM and related technologies to achieve efficient execution and improved quality
Requirements
- BS degree in technical subject area with minimum 10 years of proven experience or equivalent
- Deep knowledge of OOP, SystemVerilog and UVM
- Deep knowledge in developing scalable and portable test-benches
- Strong experience with verification methodologies and tools such as simulators, waveform viewers, Build and run automation, coverage collection, gate level simulations
- Working experience using LLMs for efficiency and quality
- Experience with power-aware (UPF) or similar verification methodology
- Excellent knowledge of one of the scripting languages such as Python, Perl, TCL
- Experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required
- Knowledge of formal verification methodology is a plus but not required
- Knowledge of emulation for verification technologies is a plus but not required
Skills
- OOP
- SystemVerilog
- UVM
- Verification methodologies
- Simulators
- Waveform viewers
- Build and run automation
- Coverage collection
- Gate level simulations
- LLMs
- Power-aware (UPF)
- Python
- Perl
- TCL
- Serial protocols
- PCIe
- USB
- Parallel protocols
- DDR
- Formal verification
- Emulation
Location
- Apple
Work Type
- Full-time
Experience Level
- 10 years of proven experience or equivalent
Education Level
- BS degree in technical subject area
About the Company
- At Apple, we work every single day to craft products that enrich people’s lives.