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About the Role
As a Sr. Verification Engineer, you will be part of a team developing MEMS timing ICs. It is not necessary to meet all job requirements to be a qualified candidate for the position.
Responsibilities
- Developing SV-RNM models for both analog and mixed-signal circuits
- Developing verification plan from chip or block specifications
- Developing UVM-based verification environment (scoreboards, monitors, sequencers, etc.)
- Developing digital-top verification in System Verilog
- Defining and writing System Verilog Assertions (SVA)
- Defining and writing functional coverages and covergroups
- Running simulations and debugging simulation results
- Reviewing verification results for Tape-out sign-off
- Communicating with stakeholders (design/test/verification) to facilitate teamwork and efficient sharing of information and exchange of ideas
Requirements
- MS (BS) degree in electrical/computer engineering or related fields with 5 (8) years of work experience doing verification in the semiconductor industry
- Good verbal and written communication skills in English
- Proficient in SystemVerilog and SystemVerilog OOP
- Fluency in utilizing scripting languages such as Perl / Python
- Proficient (through work experience) in verification using UVM
- Strong experience writing SystemVerilog Assertions (SVA)
- Understanding of Analog schematic and experience with Cadence Virtuoso
- Basic understanding of digital design using Verilog
- Ability to communicate and work effectively with geographically dispersed teams of mixed-signal, digital design and analog design engineers
- Ability to work independently and drive solutions to challenging problems
- Experience with generating functional models for analog blocks using SystemVerilog RNM, Wreal (V-AMS), or similar techniques
- Experience with UVM-AMS methodology
- Solid experience with Formal Property Verification (FPV)
- Programming experience writing OOP code in C++
- Excellent written and verbal communication skills in English
- Experience with performing analog mixed-signal verification
- Proven track record in working well with others in fast-paced and collaborative work environment
- Knowledge of analog design
- Knowledge of synthesizable digital design
- Experience working on verification of datapath designs including filters
Skills
- SystemVerilog
- SystemVerilog OOP
- Perl
- Python
- UVM
- SystemVerilog Assertions (SVA)
- Cadence Virtuoso
- Verilog
- C++
Experience Level
- 5 (8) years of work experience
Education Level
- MS (BS) degree in electrical/computer engineering or related fields
Salary/Compensations
- Eligible for a quarterly bonus tied to the achievement of innovation goals
- Equity grants
About the Company
- SiTime is the Precision Timing company.
- Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability.
- MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience.
- Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.
- Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability.
- With more than 4 billion devices shipped, SiTime is changing the timing industry.
- For more information, visit: www.sitime.com.
- Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique.
- Innovation on Top – Philosophies of Innovation with Rajesh Vashist
- Fabrication Knowledge – An Interview with Rajesh Vashist
- SiTime Corporation – YouTube
Equal Opportunity
- SiTime is committed to providing equal employment opportunities to all employees and applicants.
- Employment decisions are based on qualifications, merit, and business needs.
- We do not discriminate on the basis of any characteristic protected by applicable law.