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About the Role
Meta Reality Labs is building custom silicon for next-generation AR/VR devices. As a Design Verification Engineer, you will ensure the quality of complex custom chips that enable immersive AR/VR experiences by developing and executing verification strategies for digital logic blocks and subsystems.
Responsibilities
- Develop and own verification plans for digital logic blocks, subsystems or SoCs within custom AR/VR and AI silicon, covering functional coverage, corner cases, and compliance requirements
- Design and implement constrained-random UVM testbenches to verify complex RTL designs including processors, interconnects, memory controllers, multimedia accelerators, AI accelerators and full SoCs
- Define and close functional coverage models and code coverage metrics to ensure thorough verification of design intent
- Collaborate with cross functional teams to define verification plans and close coverage
- Develop and maintain simulation infrastructure, regression frameworks, and automated test frameworks to support continuous integration of design changes
- Perform formal verification and property checking on critical design blocks to complement simulation-based verification
- Debug failing simulations and regressions by analyzing waveforms, log files, and RTL code to root-cause design or testbench issues
- Partner with post-silicon validation and firmware teams to develop pre-silicon test content that transitions to hardware bring-up
- Contribute to verification methodology improvements, including reusable verification collaterals and shared infrastructure across the silicon team
- Track and report verification progress, coverage closure status, and risk areas to design and program management stakeholders
Requirements
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 6+ years of experience in digital design verification, including development of UVM-based constrained-random testbenches for RTL blocks, subsystems or SoCs
- 6+ years of experience with hardware description and verification languages including SystemVerilog and/or VHDL
- Experience with defining and closing functional coverage models and code coverage metrics for complex digital designs
- Experience with debugging RTL simulations using waveform analysis tools and log-based root-cause analysis
- Experience with scripting languages such as Python or Perl for test automation, regression management, or coverage analysis
Skills
- SystemVerilog
- VHDL
- UVM
- Python
- Perl
- Formal verification
- RTL simulation
- Waveform analysis
- HW/SW interoperability verification
- Firmware validation
- Post-silicon validation
- Hardware bring-up
- Low-power design verification
- Performance verification
- AI accelerators
- Security verification
- Interconnect verification
- Memory controller verification
- SoC verification
- Bare metal frameworks
Location
- Remote
Work Type
- Full-time
Experience Level
- 6+ years
Education Level
- Bachelor's degree
Salary/Compensations
- $146,000/year to $209,000/year
Benefits
- Bonus
- Equity
About the Company
- Meta Reality Labs is building custom silicon to power the next generation of augmented and virtual reality devices, including headsets and wearables.