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About the Role
Ericsson Silicon is seeking an innovative Design Verification Engineer to architect, verify, and scale custom IPs, ASICs, SoCs, and FPGA-based platforms for next-generation communications infrastructure. This role involves pioneering AI-driven verification methodologies and agentic workflows to enhance test generation, automate debug loops, and accelerate coverage closure, working closely with cross-functional teams to deliver high-quality custom silicon.
Responsibilities
- Define verification plans, environments, and schedules for complex Layer 1 accelerator ASICs, SoCs, and FPGA platforms.
- Build reusable UVM-based verification environments using SystemVerilog, integrated with LLM-assisted test generation and intelligent stimulus models.
- Utilize and develop AI agentic frameworks for autonomous regression failure triage, test sequence drafting, and log file parsing.
- Drive functional, code, and assertion coverage closure using machine learning-guided constrained-random and formal verification techniques.
- Build and maintain verification infrastructure using Python, Tcl, shell scripting, Jenkins, Git, and AI-augmented CI/CD automation pipelines.
- Verify RTL and gate-level designs across software simulation, hardware emulation, FPGA prototyping, and post-silicon environments.
- Leverage AI-assisted log analysis and pattern recognition tools for debugging across RTL, gate-level netlists, and hardware-software co-simulation platforms.
- Validate performance and functionality across custom Ericsson-Proprietary Interfaces, AMBA, PCIe, DDR, Ethernet, and high-speed SerDes.
- Contribute to verification methodology evolution by embedding generative AI and automation tools into daily workflows.
- Mentor junior engineers on foundational verification techniques and modern AI/agentic development tools.
Requirements
- Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
- 6+ years of professional design verification experience for complex ASIC, SoC, FPGA, or semiconductor products.
- Strong programming experience with SystemVerilog/Verilog.
- Hands-on expertise developing and maintaining UVM-based environments.
- Deep understanding of constrained-random verification, assertion-based verification, scoreboards, checkers, and coverage-driven signoff.
- Strong scripting and automation skills using Python, Tcl, Perl, or shell scripting.
- Experience with Git, Jenkins, and CI/CD pipelines.
- Understanding of SoC/ASIC architectures, with specific exposure to Layer 1 accelerators, DSPs, AI/ML accelerators, RISC-V, or ARM Cortex processors.
- Experience verifying standard interfaces such as AMBA AXI/AHB/APB, PCIe, DDR, Ethernet, or SerDes.
- Strong written and verbal communication skills.
- Proven track record of cross-functional collaboration.
- Practical experience integrating LLMs, custom coding assistants, or autonomous AI agents into hardware design, test generation, or debug loops.
- Experience building custom Python-based automation frameworks that interface with EDA APIs or parse large-scale regression datasets using machine learning.
- Experience with formal or semi-formal verification tools such as JasperGold.
- Knowledge of clock-domain crossing (CDC), reset-domain crossing (RDC), low-power verification (UPF/CPF), or simulation-to-silicon correlation.
- Exposure to C/C++, assembly (RISC-V/ARM), or hardware-software co-verification.
- Familiarity with Jira, Confluence, and Agile development methodologies in semiconductor environments.
Skills
- SystemVerilog
- Verilog
- UVM
- Python
- Tcl
- Perl
- Shell scripting
- Git
- Jenkins
- CI/CD
- AI
- Agentic workflows
- LLM
- Generative AI
- Machine Learning
- Formal Verification
- AMBA AXI/AHB/APB
- PCIe
- DDR
- Ethernet
- SerDes
- RISC-V
- ARM Cortex
- C/C++
- Assembly
- Jira
- Confluence
- Agile
Location
- Austin, Texas
Work Type
- Full-time
Experience Level
- 6+ years
Education Level
- Bachelor’s degree
- Master’s degree
Salary/Compensations
- The salary range for this position is dependent on various factors including, but not limited to, location, and the candidate’s combination of job-related knowledge, qualifications, skills, education, training, and experience.
- Opportunity for an annual bonus based on business and individual performance.
Benefits
- Choice of three medical plan options
- Dental plan option
- Company credits towards medical and dental premiums
- Ericsson US 401(k) Plan with automatic 3% company contribution
- Ericsson match $1 for $1 on the first 3% of eligible pay and 50 cents on the next 2% of eligible pay (up to 4% match)
- Company credits for basic life insurance and basic accidental death and dismemberment coverage
- Company credits for short-term and long-term disability coverage
- Option to participate in Ericsson’s Stock Purchase Plan
- 15 days of accrued vacation
- Up to 3 personal days per year
- 11 annual holidays
- 8 hours of volunteer time
- 80 hours of sick time annually
- Up to 16 weeks of paid maternity leave
- 6 weeks of parental or adoption leave at 100% pay
- Financial wellness programs
- Educational assistance
- Matching gifts
- Recognition programs
About the Company
- At Ericsson Silicon, you will work on mission-critical hardware programs where verification quality directly dictates the performance of global 5G and future networks.
- By combining deep hardware fundamentals with cutting-edge AI and agentic workflows, you will help redefine how high-performance custom silicon is verified, debugged, and brought to market.
Equal Opportunity
- Ericsson uses a merit-based hiring approach that values people with different experiences, perspectives and skillsets.
- We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team.
- Ericsson is proud to be an Equal Opportunity employer.