FPGA Digital Design Engineer at Kepler Communications | CA | Rezi

FPGA Digital Design Engineer at Kepler Communications

FPGA Digital Design Engineer

Kepler Communications · CA

3 weeks ago

FPGA Digital Design Engineer

Kepler Communications · CA

22 days ago
Resume preview

Impress employers and recruiters.
Choose from hundreds of resume examples.

Target Resume Now
Resume preview

Tailor your resume to this FPGA Digital Design Engineer role.

Rezi rewrites your resume against Kepler Communications's job description. Free.

Resume score gauge reading 58 out of 100

Don't guess if your resume is good enough.

See how it scores against the FPGA Digital Design Engineer posting at Kepler Communications — free, in seconds.

About the Role

Kepler is seeking a top-tier FPGA Digital Design Engineer to develop the next generation of satellites, focusing on FPGA code design and implementation for DSP algorithms or embedded systems.

Responsibilities

  • Design and implementation of FPGA code with a focus on DSP algorithms or embedded systems.
  • Participate in all phases of FPGA design flow, including Simulation, Synthesis, Place & Route, Timing Closure, and Hardware Testing.
  • Develop custom IP for new features of Kepler satellite digital payloads.
  • Iterate on current DSP and interface designs to improve reliability.
  • Work with IP core vendors to integrate new functionality into Kepler designs.
  • Develop communications and network architecture of future satellite constellations.
  • Participate in conceptual design studies of new spacecraft.

Requirements

  • Bachelor’s Degree in Computer Engineering, Electrical Engineering or equivalent.
  • 5+ years of working experience with FPGA/RTL design.
  • Proficiency in Verilog, SystemVerilog, or VHDL with the willingness to learn or pivot to SystemVerilog.
  • Experience with Xilinx FPGAs, specifically Zynq and UltraScale.
  • Solid understanding of timing principles, including clock domain crossing and timing closure.
  • Strong scripting skills (e.g., Python, Tcl, csh/bash, etc.).
  • Experience with FPGA tools (e.g., Vivado, Quartus) and HDL Simulation Tools (ModelSim).

Skills

  • FPGA/RTL design
  • Verilog
  • SystemVerilog
  • VHDL
  • Xilinx Zynq
  • Xilinx UltraScale
  • Timing principles
  • Clock domain crossing
  • Timing closure
  • Python
  • Tcl
  • csh/bash
  • Vivado
  • Quartus
  • ModelSim

Location

  • Remote

Work Type

  • Full-time

Experience Level

  • 5+ years

Education Level

  • Bachelor’s Degree in Computer Engineering, Electrical Engineering or equivalent
  • Masters of Science in Computer/Electrical Engineering, or equivalent

Salary/Compensations

  • $131,000 - $181,000 CAD

Benefits

  • Total compensation package

About the Company

  • Kepler's mission is to provide real-time on-orbit connectivity for critical missions, enabling a new era of data-driven intelligence and innovation.
  • Kepler operates the first commercial optical data relay constellation with 33 satellites launched to date, enabling real-time, continuous space communications.
  • The company supports advanced on-orbit compute and hosted payload capabilities.

Equal Opportunity

  • Kepler Communications is committed to fostering an inclusive, accessible environment, where all employees and customers feel valued, respected and supported.
  • We welcome applications from: Women, Aboriginal persons, persons with disabilities, ethnic minorities, visible minorities, people who identify as LGBTQ+ and others who may contribute to diversification in our workplace.
  • Kepler will provide accommodation during the recruitment process to ensure equal access to applicants with disabilities upon request.