Principal Application Engineer (STA - SignOff) at Cadence Design Systems | Austin, TX, US | Rezi

Principal Application Engineer (STA - SignOff) at Cadence Design Systems

Principal Application Engineer (STA - SignOff)

Cadence Design Systems · Austin, TX, US

3 weeks ago

Principal Application Engineer (STA - SignOff)

Cadence Design Systems · Austin, TX, US

24 days ago
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About the Role

We are seeking a Principal Application Engineer to provide pre-sales and post-sales technical support for Cadence's Digital Implementation and Signoff tools. This role involves collaborating with sales teams to deliver workshops, benchmarks, product demonstrations, and consultations to drive sales campaigns and ensure customer success.

Responsibilities

  • Present the technical capabilities of Cadence Digital Implementation and Signoff tools and flows to customers.
  • Identify product opportunities at existing and potential customers and collaborate with account teams to execute technical campaigns.
  • Support technical evaluations and benchmarks, driving the implementation of Cadence solutions.
  • Provide ongoing support and promote usage at existing customer sites.
  • Collaborate with R&D to improve tools and methodologies.
  • Create and contribute technical content for Cadence Online Support.
  • Travel as required (up to 20%).

Requirements

  • Strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis.
  • Experience with ASIC digital implementation flows and tools is a plus.
  • Working knowledge of a scripting language (TCL/Perl/Python).
  • Minimum BS-EE plus 8-10 years of experience or MS-EE plus 6-8 years of experience.
  • Core timing signoff expertise, advanced node STA, UPF & constraints debugging, hierarchical & 3DIC design STA and closure solutions.
  • Strong customer-facing communication and problem-solving skills.
  • Strong personal drive for continuous learning and expanding professional skill sets.
  • Strong verbal and written communication skills.

Skills

  • Digital Design Fundamentals
  • Semiconductor fundamentals
  • Static Timing Analysis
  • ASIC digital implementation flows and tools
  • TCL
  • Perl
  • Python
  • Timing signoff
  • Advanced node STA
  • UPF
  • Constraints debugging
  • Hierarchical design STA
  • 3DIC design STA
  • Customer-facing communication
  • Problem solving
  • Continuous learning
  • Verbal communication
  • Written communication

Location

  • California

Work Type

  • Full-time

Experience Level

  • 8-10 years (BS-EE)
  • 6-8 years (MS-EE)

Education Level

  • BS-EE
  • MS-EE

Salary/Compensations

  • $116,200 to $215,800

Benefits

  • Incentive compensation (bonus, equity)
  • Competitive On Target Earnings (OTE) incentive compensation structure for sales positions
  • Paid vacation
  • Paid holidays
  • 401(k) plan with employer match
  • Employee stock purchase plan
  • Medical plan options
  • Dental plan options
  • Vision plan options

About the Company

  • At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
  • We’re doing work that matters. Help us solve what others can’t.