Application Engineer Architect (STA SignOff) at Cadence Design Systems | Austin, TX, US | Rezi

Application Engineer Architect (STA SignOff) at Cadence Design Systems

Application Engineer Architect (STA SignOff)

Cadence Design Systems · Austin, TX, US

3 weeks ago

Application Engineer Architect (STA SignOff)

Cadence Design Systems · Austin, TX, US

24 days ago
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About the Role

Lead technical engagements with customers and partners to drive adoption of Cadence signoff portfolio and AgenticAI features across advanced nodes.

Responsibilities

  • Lead technical engagements with customers and partners to drive and adopt Cadence signoff portfolio.
  • Work closely with design teams to meet customer success metrics and guide adoption of Cadence’s timing signoff & closure and AgenticAI features across advanced nodes (5nm and below).
  • Partner with R&D and Product Engineering to influence tool enhancements based on real-world customer requirements.
  • Drive complex benchmarks, flow optimizations, and deployment of cutting-edge methodologies for timing sigoff & closure, STA, IR Drop, and power/timing closure.
  • Represent Cadence at industry forums, author technical papers, and deliver keynote presentations to position Cadence as a market leader.

Requirements

  • 15+ years of experience in IC design implementation and signoff, with demonstrated success in managing large-scale technical programs.
  • Deep expertise in digital design fundamentals, advanced node STA & ECOs (3nm and below), and EDA tool ecosystems.
  • Core timing signoff expertise, advanced node STA, UPF & constraints debugging, hierarchical & 3DIC design STA and closure solutions.
  • Proven track record of leading technical teams and driving customer success at executive levels.
  • Strong proficiency in scripting (Tcl, Python, Perl) and flow customization for design closure.
  • Excellent communication, negotiation, and leadership skills with the ability to influence internal and external stakeholders.
  • Prior experience with Cadence tools (Tempus, Certus, QRC) and competitive solutions highly desirable.

Skills

  • Timing signoff
  • STA
  • IR Drop
  • Power/timing closure
  • Tcl scripting
  • Python scripting
  • Perl scripting
  • UPF
  • 3DIC design STA

Location

  • Washington

Work Type

  • Full-time

Experience Level

  • 15+ years

Education Level

  • BS/MS in Electrical Engineering, Computer Engineering, or related field.

Salary/Compensations

  • $154,000 to $286,000

Benefits

  • Incentive compensation: bonus, equity
  • Paid vacation
  • Paid holidays
  • 401(k) plan with employer match
  • Employee stock purchase plan
  • Variety of medical, dental and vision plan options

About the Company

  • At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
  • We’re doing work that matters. Help us solve what others can’t.

Equal Opportunity

  • We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.