Design Verification Manager at Semtech | CA, US | Rezi

Design Verification Manager at Semtech

Design Verification Manager

Semtech · CA, US

3 weeks ago

Design Verification Manager

Semtech · CA, US

23 days ago
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About the Role

The Design Verification (DV) Manager leads a verification team, developing and implementing verification plans for mixed-signal integrated circuit blocks and systems. This role involves technical leadership, mentoring, and collaboration with cross-functional teams, reporting to engineering leadership and program management.

Responsibilities

  • Lead, mentor, and develop a geographically distributed verification engineering team across multiple projects.
  • Manage verification team deliverables, quality, schedules, and resource allocation for concurrent projects.
  • Drive the definition and implementation of comprehensive verification strategies and test plans for digital/mixed-signal IC designs at block and top levels.
  • Understand micro-architecture and specifications through close collaboration with design teams.
  • Direct detailed test plans, coverage models, and verification environments.
  • Drive coverage closure, including functional, code, and assertion-based coverage.
  • Generate technical documentation and lead verification reviews.
  • Manage the design and implementation of complex testbenches using SystemVerilog and UVM methodology.
  • Lead block and chip-level RTL, gate-level, and AMS verification.
  • Develop directed test cases, constrained-random verification environments, and reusable verification components.
  • Enhance verification scalability and portability through environment improvements and tool automation.
  • Establish and manage continuous integration, regression testing, scoreboards, monitors, and checkers.
  • Track and report verification progress using quantitative metrics and coverage analysis.
  • Identify and mitigate verification risks early.
  • Interface with system, digital hardware, embedded firmware, analog, and cross-functional teams.
  • Drive the adoption of advanced verification methodologies, best practices, and tool evaluation.
  • Provide technical support to silicon lab evaluation, test, product, and application engineers.

Requirements

  • 10+ years of industry experience in integrated circuit design verification (DV).
  • B.S. or M.S. in Electrical or Computer Engineering.
  • Experience leading, mentoring, or informally managing engineers or projects.
  • Strong analytical, synthesis, and problem-solving skills.
  • In-depth knowledge and experience in digital integrated circuit verification with MCU-based hardware systems (ARM, RISC-V, PIC, STM32) including memories, custom digital micro-architecture, interfaces, dedicated hardware peripherals, external IPs, and analog peripherals.
  • Proficiency in SystemVerilog as a high-level verification language and UVM implementation.
  • Proficiency in Verilog/VHDL.
  • Proficiency in scripting languages (Python, Perl).
  • Proficiency in debugging capabilities.
  • Proficiency with industry-leading EDA verification tools (Synopsys, Siemens, Cadence).
  • Demonstrated technical leadership.
  • Independent, self-motivated, rigorous, innovative, team player with the ability to follow through.
  • Excellent verbal and written communication skills.
  • Knowledge of system-level aspects: signal processing, mixed-signal, digital hardware, embedded firmware, analog, modeling, test, and application.
  • Experience with standard hardware protocols (I2C, I3C, SPI, MIPI).
  • Experience in mixed-signal products, design, and analog/mixed-signal (AMS) verification.
  • Experience with analog block behavioral modeling with SV RNM/Verilog/VHDL.
  • Experience with consumer and/or ITA market circuit developments.

Skills

  • SystemVerilog
  • UVM
  • Verilog
  • VHDL
  • Python
  • Perl
  • Debugging
  • EDA verification tools
  • Signal processing
  • Mixed-signal
  • Digital hardware
  • Embedded firmware
  • Analog
  • Modeling
  • Test
  • Application
  • I2C
  • I3C
  • SPI
  • MIPI
  • Analog block behavioral modeling

Location

  • San Diego, CA
  • San Jose, CA

Work Type

  • Hybrid
  • Remote (Friday)

Experience Level

  • 10+ years of industry experience in integrated circuit design verification (DV)
  • Experience leading, mentoring or informally managing engineers or projects

Education Level

  • B.S. or M.S. in Electrical or Computer Engineering

Salary/Compensations

  • USD $116,000 - $216,000

About the Company

  • Semtech Corporation is a leading supplier of analog and mixed-signal semiconductors for high-end consumer, enterprise computing, communications, and industrial equipment.
  • The Sensing Product Group has expertise in system-level platform solutions for Sensing Products including Touch & Proximity.
  • These are leading-edge low power touch-interface solutions integrated with highly accurate ADCs for enhanced sensing performance.
  • These ultra-small, feature-rich sensing systems are optimized for a wide range of battery-powered, portable applications such as smartphones, laptops, tablets, wearables, handheld devices and other consumer or industrial/telecommunications/automotive (ITA) control applications.

Equal Opportunity

  • We are proud to be an EEO employer M/F/D/V.
  • We maintain a drug-free workplace.