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About the Role

Efficient Computer is rethinking computing from the ground up to solve AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks. Join us to build the hardware and software that bring intelligence wherever it's needed and help shape the next generation of computing.

Responsibilities

Implement microarchitecture and RTL for assigned blocks in the compute fabric, on-chip networks/NoC, memory interfaces, and peripheral subsystems, working from architecture and uArch specifications.
Integrate third-party and in-house IP (RISC-V cores, NVM controllers, SRAM wrappers, I2S/I2C/APB peripherals) at the subsystem and SoC level, including bus fabric hookup and memory-mapped register interfaces.
Write and maintain uArch and design documentation for your blocks; present them in design reviews with architecture, DV, and physical design.
Own block-level front-end quality: lint-clean RTL, CDC and RDC analysis with waivers reviewed and documented, and LEC between RTL and netlist.
Run synthesis, write and maintain SDC timing constraints, and analyze STA reports; iterate on RTL to meet timing, area, and power targets.
Drive issues to closure with physical design during timing and congestion closure.
Implement low-power RTL per UPF intent: power domains, isolation, level shifters, retention, and fine-grained clock gating.
Contribute to PMU and always-on (AON) logic, such as power sequencing state machines and wakeup event aggregation.
Ensure clock-gating enables are timing-clean and CDC-correct; run RTL power analysis and act on the results.
Run block-level simulations and debug failures alongside the DV team; contribute directed test scenarios for corner cases, back-pressure, and power-state transitions.
Run and debug gate-level simulations.
Support silicon bring-up with RTL-level debug during lab validation.

Requirements

8-10 years of front-end digital design experience on processor, accelerator, or SoC products.
Significant contributions to at least two tapeout cycles.
Strong proficiency in SystemVerilog for synthesizable RTL: state machines, arbiters, FIFOs and flow control, and datapath logic.
Hands-on experience with standard VLSI front-end flows: lint, CDC/RDC, LEC, synthesis, SDC constraints, and STA, with the ability to interpret and act on their reports.
Experience with low-power RTL techniques: UPF-driven flows, clock gating, power domains, isolation, and retention.
Working knowledge of at least one on-chip bus protocol (AXI, AHB, APB, TileLink, or NoC equivalent) at the RTL level.
Experience with on-chip memories: SRAM wrappers, banking, and memory-mapped register interfaces.
Comfortable running RTL simulations and debugging with waveform tools.
Clear written and verbal communication; able to document designs and hold design reviews.
Experience designing or integrating on-chip networks, dataflow pipelines, or memory subsystems.
Familiarity with NVM controller RTL (MRAM, RRAM, etc.), including ECC and program/erase sequencing.
Experience with very low power design techniques and the RTL design choices they require.
Understanding of parallel execution models such as dataflow, SIMD, or systolic arrays.
Experience with RTL and gate-level power analysis tools and methodologies.
Exposure to DFT concepts: scan insertion, ATPG, and DFT-friendly RTL coding.
Scripting skills (Python, Tcl, Perl) to automate design flows.

Skills

SystemVerilog
VLSI front-end flows
Lint
CDC/RDC
LEC
Synthesis
SDC constraints
STA
Low-power RTL
UPF
Clock gating
Power domains
Isolation
Retention
AXI
AHB
APB
TileLink
NoC
SRAM wrappers
Memory-mapped register interfaces
RTL simulation
Waveform tools
NVM controller RTL
ECC
Dataflow
SIMD
Systolic arrays
RTL power analysis
Gate-level power analysis
DFT
Scan insertion
ATPG
Python
Tcl
Perl

Experience Level

Senior

Salary/Compensations

$180,000 to $245,000

Benefits

10% annual bonus
Meaningful equity
Comprehensive benefits
401(k) match
Company-paid benefits
Paid parental leave
Flexibility

About the Company

Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks—unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we're accelerating customer deployments and scaling our architecture to data center performance.
This is a unique opportunity to join a growing HW engineering org early and leave your mark on our products and processes as we move from initial product development to market release and scaled volume production.
Join our team and help us shape the future of computing at the edge and beyond!
Build what's next. At Efficient, you'll tackle big challenges with room to take ownership and make an impact. We back you with competitive pay, equity, a 401(k) match, company-paid benefits, paid parental leave, and flexibility—plus opportunities to grow your skills and career as we scale.