Senior Digital Verification Engineer - Contract at Efficient Computer | Austin, TX, US | Rezi

Senior Digital Verification Engineer - Contract at Efficient Computer

Senior Digital Verification Engineer - Contract

Efficient Computer · Austin, TX, US

3 weeks ago

Senior Digital Verification Engineer - Contract

Efficient Computer · Austin, TX, US

24 days ago
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About the Role

Efficient Computer is seeking a senior Digital Verification contractor to own the verification of complex blocks and subsystems within their SoC, including proprietary Fabric technology. This role involves joining a new Verification & Emulation team, collaborating with RTL designers and architects, and independently developing and driving UVM environments to coverage closure.

Responsibilities

  • Own verification of assigned blocks and subsystems from spec review through coverage sign-off.
  • Write and review verification plans based on design and architecture specifications.
  • Architect, build, or extend UVM/SystemVerilog testbenches, including agents, scoreboards, reference models, sequences, and constrained-random tests.
  • Write SystemVerilog assertions and functional coverage models, and drive functional and code coverage to closure.
  • Debug complex simulation failures and collaborate with RTL designers to resolve bugs.
  • Clearly report verification status, risks, and coverage gaps to the DV lead and design team.
  • Document the verification environment for future maintenance by the full-time team.

Requirements

  • Bachelor's or Master's/PhD in Electrical Engineering, Computer Engineering, or a related field.
  • 8+ years of ASIC/SoC design verification experience, with multiple projects completed through tapeout.
  • Expertise in UVM testbench architecture and SystemVerilog for verification (classes, constraints, interfaces, functional coverage, SVA).
  • Proven track record of driving functional and code coverage to sign-off on multi-million-gate designs.
  • Strong ability to independently debug complex simulation failures using industry-standard tools (VCS/Verdi, Xcelium, or Questa).
  • Proficiency in Python for regression automation, log analysis, and coverage post-processing.
  • Ability to quickly learn new designs and deliver with minimal supervision.
  • Clear written and verbal communication skills for reporting status, risks, and tradeoffs.

Skills

  • UVM
  • SystemVerilog
  • SVA
  • Python
  • VCS/Verdi
  • Xcelium
  • Questa
  • C/C++
  • Formal verification
  • JasperGold
  • UPF

Work Type

  • Contract

Experience Level

  • Senior
  • 8+ years

Education Level

  • Bachelor's degree
  • Master's degree
  • PhD

Salary/Compensations

  • $80–$130 per hour

Benefits

  • Competitive pay
  • Equity
  • 401(k) match
  • Company-paid benefits
  • Paid parental leave
  • Flexibility

About the Company

  • Efficient Computer is rethinking computing to solve AI's energy challenges with its Fabric architecture, offering significant energy efficiency improvements. Their first processor, Electron E1, is shipping, and they have secured substantial funding to scale their architecture. They aim to build hardware and software that bring intelligence to various applications and shape the future of computing.