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About the Role

The Design Verification Engineer will interface with various teams at Apple, gaining knowledge of numerous chips and platforms to integrate system-level understanding into the verification flow. Responsibilities span from specification to signoff, including strategy definition, execution, performance analysis, and quality metric management.

Responsibilities

Define comprehensive property sets for functional coverage of hardware models.
Formalize verification properties using SVA.
Execute formal proofs and analyze convergence behavior (accuracy vs. execution time).
Document methodology and best practices for the verification flow.

Requirements

Currently enrolled in Computer Science or equivalent.
Knowledge of formal verification techniques.
Knowledge of Verilog and/or VHDL.
Passionate about mathematics, with good mathematical/analytical sense.
Scripting language knowledge (perl/python).
Good written and verbal communication skills.
Experience in working with international teams.

Skills

Formal verification
Verilog
VHDL
SVA
Perl
Python
Mathematical analysis

Location

London

Work Type

Full-time

Experience Level

Internship

Education Level

Master's / Bachelor's in Computer Science or equivalent

About the Company

Apple is a rapidly growing company where new ideas and complex challenges lead to phenomenal products, services, and customer experiences.
The AMS IP team owns a wide portfolio of IPs and complete subsystems used in all Apple products.