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About the Role

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

Responsibilities

Architecture exploration
Micro-architecture development
Soft and hard IP identification, selection and integration
Collaboration with verification and emulation teams in test plan development and debug
Collaboration with implementation team to close the design on timing and power

Requirements

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
PhD degree in computer science, computer engineering, a relevant technical field, and/or equivalent practical experience
Experience in micro-architecture and RTL development for complex control and data path IPs or experience in SoC micro-architecture, design and integration
RTL development using Verilog, SystemVerilog and HLS

Skills

Verilog
SystemVerilog
HLS
Data path development
CPU
NOC
Memory and Peripheral Subsystems
Synthesis
Timing Closure
Formal Verification Methodology

Education Level

Bachelor's degree
PhD degree

Salary/Compensations

$114,000/year to $172,000/year

Benefits

bonus
equity
benefits