Impress employers and recruiters.
Choose from hundreds of resume examples.
Impress employers and recruiters.
Choose from hundreds of resume examples.
Tailor your resume to this ASIC Design Verification Engineer, DFT role.
Rezi rewrites your resume against Meta's job description. Free.
Tailor your resume to this ASIC Design Verification Engineer, DFT role.
Rezi rewrites your resume against Meta's job description. Free.
Don't guess if your resume is good enough.
See how it scores against the ASIC Design Verification Engineer, DFT posting at Meta — free, in seconds.
Don't guess if your resume is good enough.
See how it scores against the ASIC Design Verification Engineer, DFT posting at Meta — free, in seconds.
About the Role
Meta is seeking an experienced ASIC Design Verification Engineer specializing in Design for Testability (DFT) to join the Infrastructure Silicon organization. This role involves developing and verifying DFT architectures for custom ASICs and SoC designs powering Meta's data center infrastructure, driving DFT verification closure across all levels to ensure silicon manufacturability, testability, and quality for first-pass success.
Responsibilities
- Define and implement DFT verification plans covering scan insertion, ATPG, BIST, JTAG, and boundary scan structures at IP, sub-system, and SoC levels.
- Develop and maintain UVM-based and C/C++-based testbenches to verify DFT logic, including scan chains, memory BIST, and logic BIST controllers.
- Drive verification closure using defined metrics including functional coverage, code coverage, and DFT-specific structural coverage goals.
- Collaborate with DFT architects and design engineers to review DFT insertion methodologies and validate correctness of scan stitching and test access mechanisms.
- Debug and root-cause functional and structural failures in DFT logic, working closely with design and ATPG teams to resolve issues pre-silicon.
- Develop and validate ATPG test pattern generation flows, ensuring pattern quality and fault coverage targets are met.
- Apply formal verification techniques to prove correctness of DFT control logic, scan enable paths, and test mode isolation.
- Partner with emulation and post-silicon validation teams to enable DFT bring-up and correlate pre-silicon verification results with silicon test outcomes.
- Build and maintain verification infrastructure, scripts, and automation flows to improve DFT verification efficiency and reuse across projects.
- Contribute to continuous improvement of DFT verification methodologies, tools, and best practices across the infrastructure silicon team.
Requirements
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
- 8+ years of hands-on experience in ASIC design verification using SystemVerilog and UVM-based methodologies.
- 8+ years of experience with DFT verification, including scan insertion, ATPG pattern validation, BIST verification, and JTAG/IEEE 1149.1 test access mechanisms.
- Experience with EDA tools for DFT insertion, ATPG, and simulation.
- Scripting proficiency in Python, Tcl, Perl, or Shell for verification flow automation.
- Experience driving IP, sub-system, or SoC-level verification closure including test planning, testbench development, and coverage analysis.
- Experience with formal verification techniques applied to DFT control logic, scan enable paths, or test mode isolation.
- Experience with DFT verification for AI/ML accelerator or networking ASIC designs in data center environments.
- Experience verifying high-speed interface DFT structures such as PCIe, HBM, DDR, or Ethernet SerDes.
- Experience with emulation platforms for DFT bring-up and pre-silicon to post-silicon correlation.
Skills
- ASIC design verification
- SystemVerilog
- UVM
- DFT verification
- Scan insertion
- ATPG pattern validation
- BIST verification
- JTAG
- IEEE 1149.1
- EDA tools
- Python
- Tcl
- Perl
- Shell scripting
- Formal verification
- Emulation platforms
Location
- Data Center
Work Type
- Full-time
Experience Level
- 8+ years
Education Level
- Bachelor's degree
Salary/Compensations
- $178,000/year to $250,000/year
Benefits
- bonus
- equity
- benefits
About the Company
- Meta's Infrastructure Silicon organization designs and verifies custom ASICs and SoC designs powering Meta's data center infrastructure.