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About the Role
Meta is seeking an ASIC Implementation Engineer to join our Infrastructure Silicon team, focused on building custom silicon for data center applications. This role involves developing and maintaining CAD methodologies, flows, and automation scripts for ASIC implementation, from RTL through physical design signoff. You will collaborate with design, physical design, and verification engineers to ensure efficient, high-quality tape-outs of Meta's next-generation infrastructure chips.
Responsibilities
- Design, develop, and maintain production-level CAD platforms and web-based design tooling for interactive silicon architecture exploration, floorplan visualization, and automated engineering analysis.
- Build runtime-optimized data models, algorithms, and Python APIs for large-scale design data (netlist, LEF/DEF, pin/track, and connectivity databases), achieving significant runtime improvements.
- Develop tooling for generating SOC floorplans at chip, subsystem, and block levels, driving early floorplan exploration, block shaping, and area/dimension estimation.
- Develop debug features for logical and physical connectivity and beachfront analysis on DEF and netlist data, evaluating pin locations, port configurations, and connectivity consistency.
- Develop automation and methodology across all FE tools (Synthesis, Physical Design, STA, Power, Floorplanning, Connectivity Analysis, Pin Planning).
- Partner with Design, DV, Architecture, and Physical Design engineers on handoffs and timing/congestion/connectivity feedback.
Requirements
- Currently have, or be in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
- 2+ years of experience in synthesis & physical design.
- Proficiency in Python for algorithm development, engineering analysis, and automation.
- Experience developing CAD/EDA tools, flows, or engineering automation.
- Experience with RTL synthesis, physical design and PPA optimization.
- Knowledge of front-end and back-end ASIC tools.
- Experience working across cross-functional teams and vendors to debug timing, area, and power issues.
Skills
- Python
- RTL synthesis
- Physical design
- PPA optimization
- Front-end ASIC tools
- Back-end ASIC tools
- DEF
- Netlists
- Floorplanning data
- Pin definition generation
- PG-aware pin placement
- Data structures
- Algorithms
- Computational geometry
- Performance optimization
- Multi-chiplet connectivity
- Feedthrough evaluation
- Clock/voltage/reset domains
- 2.5D/3D SoIC assembly
- Verilog netlist parsing
- LEF/DEF parsing
- Liberty parsing
- SDC parsing
- Web-based engineering applications
- Interactive visualization frameworks
- Client-server architecture
- Session and state management
Location
- USA
Work Type
- Full-time
Experience Level
- 2+ years
Education Level
- Bachelor's degree
Salary/Compensations
- $114,000/year to $172,000/year
Benefits
- bonus
- equity
- benefits
About the Company
- Meta is building the future of connection through innovative technologies and platforms.