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About the Role
Cadence Solutions (North America) is seeking an experienced candidate to lead Front End Design projects, driving innovation and technical excellence in the semiconductor industry.
Responsibilities
- Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment.
- Define and develop microarchitectural features for IPs and subsystems, ensuring they meet PPA goals.
- Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic.
- Oversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and other quality checks.
- Work closely with cross-functional teams, including Design Verification (DV), Physical Design (PD), Architecture, and firmware engineers, to ensure successful delivery.
Requirements
- 10+ years of Front End design and/or verification with a BS/MS Engineering or Computer Sciences.
- Proven experience in leading and managing complex engineering projects.
- Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration.
- Expert in RTL design (Verilog), simulators debuggers.
- Hands-on experience in Synthesis, SDC creation and support PD and STA teams.
- Experience in driving results in a multi-disciplinary organization.
Skills
- RTL design
- Verilog
- SystemVerilog
- VHDL
- Simulators debuggers
- Synthesis
- SDC creation
- Front end toolset
Location
- North America
Work Type
- Full-time
Experience Level
- 10+ years
Education Level
- BS/MS Engineering or Computer Sciences
About the Company
- At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- We’re doing work that matters. Help us solve what others can’t.