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About the Role
As a Senior Design Verification Engineer, you will ensure the functional correctness and performance of digital modem designs for low-power wireless products. You will develop verification strategies, build test environments, and debug complex issues across PHY/MAC layers, contributing from design through silicon bring-up.
Responsibilities
- Define and execute verification strategies for digital modem designs across key wireless use cases
- Develop and maintain scalable verification environments using SystemVerilog/UVM or similar methodologies
- Create test plans, test benches, and stimuli to achieve high functional and coverage closure
- Debug and analyze design issues, working closely with design and architecture teams to resolve them
- Track and drive functional and code coverage to ensure verification completeness
- Collaborate cross-functionally with firmware, validation, and system teams to ensure correct system behavior
- Support silicon bring-up and correlate pre-silicon verification with post-silicon results
- Continuously improve verification methodologies, tools, and automation workflows
Requirements
- BSEE/CE or a related field
- Solid understanding of digital design fundamentals and verification concepts
- 3-6 years of experience in digital design verification, with a focus on modem or wireless PHY designs preferred
- Experience with SystemVerilog and UVM or similar verification methodologies
- Strong debugging skills with experience analyzing simulation results and identifying root causes
- Familiarity with scripting languages such as Python or Perl for automation
- Basic understanding of wireless communication systems or digital signal processing concepts
- Strong problem-solving skills and ability to work effectively in a collaborative team environment
- Experience verifying wireless standards such as BLE, Wi-Fi, Zigbee, or similar technologies
- Experience with advanced verification techniques such as constrained-random, coverage-driven verification, and SystemVerilog assertions (SVA)
- Familiarity with C/C++ or MATLAB for algorithm modeling and reference model development
- Experience with mixed-signal or system-level verification, including co-simulation with analog/RF components
- Exposure to post-silicon validation, lab bring-up, and correlation with pre-silicon results
- Experience with low-power design verification and power-aware methodologies
Skills
- SystemVerilog
- UVM
- Python
- Perl
- BLE
- Wi-Fi
- Zigbee
- SystemVerilog assertions (SVA)
- C/C++
- MATLAB
Location
- Austin, Texas
Work Type
- Full-time
Experience Level
- Senior
- 3-6 years
Education Level
- BSEE/CE or related field
Salary/Compensations
- $124,600 - $231,400 USD
Benefits
- Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental & vision plans
- Flexible vacation plan
- Highly competitive salary
- 401k plan with match and Roth plan option
- Equity rewards (RSUs)
- Life/AD&D and disability coverage
- Flexible spending accounts
- Adoption assistance
- Back-Up childcare
- Additional benefit options (Commuter benefits, Legal benefits, Pet insurance)
- 3 paid volunteer days per year
- Charitable contribution match
- Tuition reimbursement
- Monthly wellness offerings
- Free snacks
- Monthly company updates with our CEO
About the Company
- Silicon Labs is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives.
- Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications.
- Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets.
Equal Opportunity
- Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.