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About the Role

Fortaegis is a fast-scaling, highly ambitious, and cutting-edge semiconductor company seeking a Digital Design Engineer. This role is responsible for architecting, developing, and integrating RTL and IP for FPGA and ASIC-based products, translating system requirements into high-quality, reusable digital designs that meet performance goals and integrate smoothly. We seek candidates with an exceptional skillset and mindset, willing to go above and beyond.

Responsibilities

Design and implement RTL (SystemVerilog/Verilog, VHDL) based on system-level requirements, including microarchitecture documents, block diagrams, and interface specifications.
Develop, integrate, and maintain custom and third-party IP (e.g., networking, memory controllers, PCIe, high-speed SerDes), and evaluate IP for functionality, performance, area/resource usage, and integration risk.
Integrate IP and subsystems at the block and top level, including bus fabrics (e.g., AXI), clocking, reset, and CDC strategy.
Run synthesis and implementation flows (FPGA or ASIC), develop timing constraints (SDC/XDC), and drive timing closure, area, and power optimization.
Perform RTL quality checks (lint, CDC/RDC) and support verification through unit-level testbenches, assertions, and failure debug, as well as simulation, emulation, and hardware bring-up.
Coordinate with verification, architecture, hardware, software, and firmware teams on register maps, integration requirements, and design reviews to ensure smooth integration of designs.
Stay up-to-date with design tools, methodologies, and best practices, and contribute to architecture and flow improvements.

Requirements

5+ years of experience in digital design and RTL development for FPGA and/or ASIC.
Advanced knowledge of SystemVerilog and/or Verilog (VHDL a plus).
Proven experience developing and integrating IP in complex SoC or FPGA-based systems, including standard interfaces (e.g., AXI/AXI-Stream, PCIe, Ethernet, DDR, SerDes).
Hands-on experience with synthesis and implementation EDA tools (e.g., Vivado, Synopsys, Cadence).
Strong understanding of static timing analysis, CDC, and low-power techniques.
Working knowledge of verification methodologies and simulators (e.g., UVM, cocotb, SVA; Siemens, Cadence, Synopsys).
Scripting for automation (Python, Tcl, Perl).
Strong analytical and problem-solving abilities with keen attention to detail.
Ability to translate system requirements into reusable RTL and IP while weighing trade-offs among performance, area, power, and schedule.
High-speed networking (Ethernet, PCIe) or cryptographic IP experience is advantageous.
Experience with IP evaluation or vendor engagement is a plus.
Effective communication and teamwork skills.
Ability to collaborate across functions.
Ability to take ownership and solve problems beyond the scope of the job description.
Flexible, solution-oriented mindset.

Skills

SystemVerilog
Verilog
VHDL
AXI/AXI-Stream
PCIe
Ethernet
DDR
SerDes
Vivado
Synopsys
Cadence
Static timing analysis
CDC
Low-power techniques
UVM
cocotb
SVA
Python
Tcl
Perl

Experience Level

5+ years of experience

About the Company

Fortaegis is a fast-scaling, highly ambitious and cutting-edge semiconductor company.
The successful candidate will have the unique opportunity to participate in shaping the future of our visionary company, contributing to the development of ultra-secure and high-performance products.
They will be part of a dynamic and innovative team, working in a collaborative and technically rewarding environment at the forefront of semiconductor technology.