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About the Role

We are seeking an experienced Performance Modeling Engineer to drive architectural exploration, performance analysis, and system-level optimization for next-generation processors, AI accelerators, and SoC platforms. The ideal candidate will have deep expertise in processor architecture, memory systems, cache hierarchies, coherent interconnects, and transaction-level modeling (TLM). In this role, you will work closely with architecture, RTL, verification, software, and system teams to develop high-fidelity performance models, evaluate architectural tradeoffs, and guide key design decisions from concept through silicon.

Responsibilities

• Develop and maintain transaction-level and analytical performance models for processors, memory hierarchies, interconnects, and accelerators.
• Create detailed models of cache hierarchies, coherent interconnects, memory subsystems, DMA engines, and shared-memory multiprocessor (SMP) systems.
• Evaluate architectural tradeoffs involving performance, power, area, latency, bandwidth, and scalability.
• Analyze workload behavior and identify system bottlenecks through simulation and modeling.
• Drive architectural studies for next-generation multicore and cache-coherent systems.
• Perform deep performance analysis of branch prediction, hardware prefetching, speculative execution, load/store architectures, cache coherence protocols, and memory consistency models.
• Model and validate the behavior of multithreaded and multiprocessor workloads.
• Collaborate with hardware and software teams to correlate performance models with RTL simulations, emulation results, and silicon data.
• Present architectural recommendations and performance insights to engineering leadership.

Requirements

• BS, MS, or PhD in Computer Engineering, Electrical Engineering, Computer Science, or related field.
• 10+ years of industry experience in computer architecture, microarchitecture, or performance modeling.
• Strong understanding of processor architecture and microarchitecture, cache and memory hierarchy design, shared-memory multiprocessor (SMP) systems, and multicore scaling challenges.
• Experience developing Transaction-Level Models (TLM/SystemC), analytical performance models, and architectural simulators.
• Deep knowledge of cache behavior, including capacity and conflict effects, latency analysis, prefetching techniques, memory locality, and coherence interactions.
• Familiarity with modern cache coherence protocols such as ARM CHI, ACE, and MESI/MOESI-based protocols.
• Strong understanding of memory consistency models, atomic operations, synchronization mechanisms, and ordering semantics.
• Strong software development skills in C++, Python, or equivalent languages.

Skills

• Performance Modeling
• Transaction-Level Modeling (TLM/SystemC)
• Cache Modeling
• Cache Coherence
• ARM CHI
• Processor Architecture
• SMP Architectures
• Multicore Systems
• Memory Consistency Models
• Branch Prediction
• Hardware Prefetching
• Speculative Execution
• Interconnect and NoC Modeling
• Memory System Architecture
• AI Accelerator Architecture
• Performance and Power Analysis

Experience Level

• 6+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience with a Bachelor's degree
• 5+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience with a Master's degree
• 4+ years of Software Engineering, Electrical Engineering, Systems Engineering, or related work experience with a PhD
• 2+ years of experience with high-performance microprocessor design

Education Level

• Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field
• Master's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field
• PhD in Electrical Engineering, Computer Science, Computer Engineering, or related field

Salary/Compensations

• $191,800.00 - $287,800.00

Benefits

• Competitive annual discretionary bonus program
• Opportunity for annual RSU grants
• Highly competitive benefits package

About the Company

• Qualcomm is an equal opportunity employer.
• Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Equal Opportunity

• Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.