Impress employers and recruiters.
Choose from hundreds of resume examples.
Impress employers and recruiters.
Choose from hundreds of resume examples.
Tailor your resume to this Principal Design Engineer role.
Rezi rewrites your resume against Cadence Design Systems's job description. Free.
Tailor your resume to this Principal Design Engineer role.
Rezi rewrites your resume against Cadence Design Systems's job description. Free.
Don't guess if your resume is good enough.
See how it scores against the Principal Design Engineer posting at Cadence Design Systems — free, in seconds.
Don't guess if your resume is good enough.
See how it scores against the Principal Design Engineer posting at Cadence Design Systems — free, in seconds.
About the Role
We are looking for leaders and innovators to make an impact on the world of technology.
Responsibilities
- Define the overall verification strategy, including methodology, tools, and infrastructure.
- Design scalable, reusable, and robust verification environments, including BFMs, monitors, scoreboards, and checkers.
- Analyze architectural specifications to identify critical features and corner cases for testing.
- Technically lead DV execution of small to mid-sized customer ASIC projects and handle customer interactions.
- Convert high-level customer requirements into DV execution plans.
- Write complex test cases and sequences to achieve high functional coverage.
- Lead root-cause analysis of complex design bugs and collaborate with design engineers on fixes.
- Implement constrained-random stimulus generation to explore the design space.
- Utilize formal tools to prove properties or find bugs.
- Monitor and analyze functional and code coverage metrics.
- Oversee gate-level simulations to verify timing and reset behavior.
- Define the 'definition of done' and provide final technical approval for the verification phase.
- Guide junior engineers on coding standards and debugging techniques.
- Act as the primary technical point of contact between design, architecture, and emulation teams.
- Manage timelines, identify risks in the verification schedule, and prioritize tasks to meet project deadlines.
Requirements
- 8–10 years of hands-on DV experience in semiconductor/ASIC/SoC companies
- Experience with industry-standard simulators: Xcelium, VCS, Questa
- Hands-on experience with formal verification tools and flows
- Experience with bus protocols such as AXI, AHB, APB, PCIe, DDR, or similar
- Familiarity with low-power verification (UPF/CPF) and gls/power-aware gls simulation
Skills
- SystemVerilog
- UVM (Universal Verification Methodology)
- Digital design fundamentals — RTL, timing, clocking, resets
- Coverage-driven verification — functional, code, and toggle coverage
- Debug skills — waveform analysis (Verisium, SimVision)
Experience Level
- 8–10 years
Education Level
- B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field
About the Company
- At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- We’re doing work that matters. Help us solve what others can’t.