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Define the overall verification strategy, including the choice of methodology (typically UVM/SystemVerilog), tools, and infrastructure.
Design scalable, reusable, and robust verification environments, including developing Bus Functional Models (BFMs), monitors, scoreboards, and checkers.
Analyze architectural specifications to identify critical features and corner cases requiring rigorous testing.
Write complex test cases and sequences to achieve high functional coverage.
Lead the root-cause analysis of complex design bugs, collaborating closely with design engineers to implement fixes.
Implement constrained-random stimulus generation to explore the design space beyond directed tests.
Utilize formal tools to prove specific properties or find deep-seated bugs that simulation might miss.
Monitor and analyze functional and code coverage metrics.
Oversee simulations on the synthesized netlist to verify timing and reset behavior.
Define the "definition of done" and provide final technical approval for the verification phase.
Guide junior engineers on coding standards and debugging techniques.
Act as the primary technical point of contact between the design, architecture, and emulation teams.
Manage timelines, identify risks in the verification schedule, and prioritize tasks to meet project deadlines.

Lead Design Engineer at Cadence Design Systems

Lead Design Engineer