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About the Role
As a Principal ASIC Design Engineer, you will take a leadership role in defining, implementing, and delivering critical IP blocks and subsystems for Positron.ai’s inference ASICs/SoCs. You will own the microarchitecture from high-level concept through RTL signoff, collaborating across architecture, verification, and physical design to achieve ambitious PPA and schedule goals. In addition to hands-on SystemVerilog design, you will mentor junior engineers, influence methodology, and drive key architectural tradeoffs that impact silicon performance and efficiency.
Responsibilities
- Define and document microarchitecture for complex IP blocks/subsystems.
- Deliver production-quality, parameterized SystemVerilog RTL with well-defined interfaces, power/clock intent, and embedded assertions.
- Lead lint, CDC/RDC, DFT integration, and synthesis bring-up; collaborate with PD on floorplan and timing closure.
- Own PPA metrics for assigned blocks and drive microarchitectural optimizations to meet targets.
- Architect and integrate high-performance interconnects (AXI/CHI/ACE), DMA engines, coherency logic, and high-speed memory interfaces (HBM/DDR).
- Engage with IP vendors and internal stakeholders to ensure seamless integration.
- Develop and enforce coding guidelines, reusable IP packaging, and signoff checklists.
- Contribute automation flows (Python/Tcl/Make/CI) to improve team efficiency.
- Partner closely with Verification to define test plans and reference models.
- Work with Architecture and Performance teams to correlate models against RTL.
- Support bring-up, post-silicon debug, and customer engagements as required.
- Guide junior engineers in design techniques, methodology, and problem-solving.
- Lead design reviews, drive consensus on tradeoffs, and advocate for best-in-class solutions.
Requirements
- BS/MS in EE/CE (or related) with 8+ years of ASIC/SoC RTL design experience on complex, high-performance silicon.
- Proven track record of leading designs from spec → microarchitecture → RTL → signoff with strong PPA outcomes.
- Deep SystemVerilog RTL expertise, including clocking, resets, CDC/RDC handling, and protocol correctness.
- Extensive experience with front-end flows/tools (lint, CDC, synthesis/STA, DFT) using major EDA suites.
- Hands-on expertise with at least three of: HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache/memory hierarchies, high-throughput datapaths.
- Strong cross-functional communication skills, capable of leading technical discussions and producing clear specifications.
Skills
- SystemVerilog
- Lint
- CDC/RDC
- DFT
- AXI/CHI/ACE
- HBM/DDR
- Python
- Tcl
- Make
- CI
- AI/ML accelerator design
- Formal verification/SVA
- Low-power design techniques
- UPF/CPF
- cocotb/UVM
- RISC-V subsystems
- Coherence protocols
Location
- Remote
Work Type
- Full-time
Experience Level
- Principal
- Senior
Education Level
- BS/MS in EE/CE (or related)
Salary/Compensations
- $225,000 – $350,000
Benefits
- Competitive salary + equity
- Comprehensive benefits
- Flexible work environment
About the Company
- Shape the next generation of AI inference hardware with a high-caliber, collaborative team.
- Take technical ownership of critical silicon components that directly impact product success.
- Opportunities to innovate, lead, and grow your influence in a rapidly evolving space.
Equal Opportunity
- Equal Opportunity Employer.
- If you’re excited about the role but don’t meet every bullet, we’d still love to hear from you.