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About the Role
The Design for Manufacturability (DFM) team focuses on technology transfer, product optimization, new product introductions, yield improvement, process margin improvement, and performance enhancement. As part of the Advanced Node Technology Development team, you will provide Design Verification for products in a high-volume production environment and optimize newer products introduced exclusively at Samsung Austin Semiconductor.
Responsibilities
- Collaborate with internal teams and customer's design teams to develop new offerings of devices, pcell, and standard cell libraries.
- Lead projects related to design risk assessment of new product introductions.
- Analyze yield to design correlations for yield improvement and other KPI improvements.
- Use EDA software to analyze & design, including extracting netlists, timing analysis, and redundancy checks.
- Consult and guide the fabrication team on possibilities of margin improvements.
- Lead or participate in devising solutions/methodology to fix/avoid future vulnerabilities in the design.
- Write SVRF/tcl code for design risk assessment.
- Develop methodology and automation scripts using bash-shell, python, tcl, etc.
- Communicate technical information to senior leadership outside of the department through presentations.
- Complete other duties as assigned.
Requirements
- Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Physics, Chemistry, Chemical Engineering, or Materials Science with experience in design verification.
- Experience with Cadence Virtuoso or other EDA experience in at least one of the following tools: Calibre, Yield Explorer, StarRC/xRC, ICC2 & TCAD.
- Working knowledge of the design-to-mask workflow (schematic, simulation, layout, physical verification, GDSII, mask).
- 300mm 16nm/14nm/10nm nodes (or below) wafer manufacturing technology experience is preferred.
- Strong scripting experience in tcl, bash/shell, or python.
- Applicants must be authorized to access information subject to U.S. export control laws or eligible for government authorization.
- Agree not to disclose to Samsung or induce or encourage Samsung to use any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.
Skills
- Design Verification
- EDA software
- Cadence Virtuoso
- Calibre
- Yield Explorer
- StarRC/xRC
- ICC2
- TCAD
- Schematic
- Simulation
- Layout
- Physical Verification
- GDSII
- Mask
- tcl
- bash/shell
- python
Location
- Austin, Texas
Work Type
- Full-time
- On-site
Education Level
- Bachelor's degree
- Master's degree
- PhD degree
Salary/Compensations
- $106,000 - $145,000
Benefits
- Medical, dental, and vision insurance
- Life insurance
- 401(k) matching with immediate vesting
- Onsite café(s)
- Workout facilities
- Paid maternity and paternity leave
- Paid time off (PTO)
- 2 personal holidays
- 10 regular holidays
- Wellness incentives
- MBO bonuses
About the Company
- Samsung is a world leader in advanced semiconductor technology, founded on the belief that the pursuit of excellence creates a better world.
- At Samsung Austin Semiconductor, we are Innovating Today to Power the Devices of Tomorrow.
Equal Opportunity
- Samsung Electronics America, Inc. and its subsidiaries are committed to Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.