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About the Role
Join the Design Technology Platform (DTP) organization within Intel Foundry to drive the development of methodologies, physical layouts, and silicon platforms for next-generation semiconductor technologies. As a member of the X-Chip Full-Chip Integration team, you will develop custom layout methodologies, lead full-chip physical integration, and drive physical verification and tapeout execution for advanced testchip and silicon lead vehicles on cutting-edge process technologies. This role is for engineers passionate about custom layout design, advanced-node physical design methodologies, and solving complex physical integration challenges, working at the intersection of technology development, physical design, verification, and manufacturing.
Responsibilities
- Lead full-chip floorplanning, physical integration, and tapeout activities for advanced-node silicon development vehicles.
- Develop and enhance custom layout methodologies and physical design flows.
- Drive physical verification closure, including DRC, LVS, DFM, density, and antenna rule compliance.
- Collaborate with Technology Development, PDK, and EDA teams to implement scalable and manufacturable design solutions.
- Analyze advanced-node design rules and contribute to design enablement for emerging process technologies, including FinFET and Gate-All-Around (GAA) architectures.
- Develop automation solutions using Tcl, Python, SKILL, or similar scripting languages to improve design productivity and quality.
- Coordinate cross-functional activities to ensure tape-in readiness, database integrity, and successful project execution.
Requirements
- Masters' degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of industry experience, OR a PhD’s degree in the same field with 1+ years of industry experience.
- Custom/analog/mixed-signal layout design experience in advanced technology nodes.
- Front-end (FEOL) layout design rules, transistor-level matching, parasitic layout concepts, and custom silicon structures.
- Debugging skills in physical verification (LVS, DRC, and DFM) using industry-standard verification engines (such as Calibre or ICV), with a proven ability to solve complex, systemic layout errors.
- Experience with Tcl, Python, or SKILL to automate layout creation, checking, and full-chip database manipulation.
- Experience with top-level floorplanning, RDL/bump planning, or backside power delivery (PowerVia) implementation.
- Proven track record of collaborating with PDK and Technology Development teams on design rule definitions, test structure vehicles, or DRC suppression strategies.
- Experience managing physical tapeout schedules, IP tracking matrices, and formal physical design Quality Assurance (QA) flows.
- Familiarity with custom layout environments (such as Cadence Virtuoso) and translating custom databases into full-chip NDM flows.
- Previous related work experience in a semiconductor foundry preferred.
Skills
- Custom layout design
- Advanced-node physical design methodologies
- Physical integration
- Physical verification
- Tapeout execution
- FinFET
- Gate-All-Around (GAA) architectures
- Tcl
- Python
- SKILL
- DRC
- LVS
- DFM
- Cadence Virtuoso
Location
- Hillsboro, Oregon
- Chandler, Arizona
- Austin, Texas
Work Type
- Hybrid
Experience Level
- 4+ years of industry experience (with Masters)
- 1+ years of industry experience (with PhD)
Education Level
- Masters' degree in Electrical Engineering, Computer Engineering, or a related field
- PhD’s degree in Electrical Engineering, Computer Engineering, or a related field
Salary/Compensations
- $122,440.00-232,190.00 USD
Benefits
- Competitive pay
- Stock bonuses
- Health benefits
- Retirement benefits
- Vacation benefits
About the Company
- Intel Foundry drives the development of methodologies, physical layouts, and silicon platforms that enable next-generation semiconductor technologies.
- Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.
- Intel offers a total compensation package that ranks among the best in the industry.
Equal Opportunity
- All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.