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About the Role
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.
Responsibilities
- Digital design and development (RTL) working in close collaboration with Multi-site leads across US and India
- Developing the micro architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoC
- Design and implement defined tasks independently
- Work in close coordination with Systems, Verification, SoC team , SW team, PD & DFT teams to get the goals completed
- Analyze reports/waivers or run various tools : Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc.
Requirements
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
- PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- Candidate will be responsible for design/developing next generation power control systems.
- Candidate will be working on ASIC based on the latest technology nodes.
- This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, RTL design along with interactions with verification, Synthesis & PD teams for design convergence.
Skills
- 5 to 8 years of strong experience in digital front end design for ASICs
- Expertise in RTL coding in Verilog/VHDL/SV of complex designs with multiple clock domains and multiple power domains
- Familiar with UPF and power domain crossing
- Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI
- Experience in low power design methodology and clock domain crossing designs
- Experience in Spyglass Lint/CDC checks and waiver creation
- Experience in formal verification with Cadence LEC
- Understanding of full RTL to GDS flow to interact with DFT and PD teams
- Expertise in Perl, TCL language
- Expertise in post-Si debug is a plus
Location
- US
- India
Work Type
- Full-time
Experience Level
- Sr Engineer
- Staff Engineer
Education Level
- Bachelor's degree in Science, Engineering, or related field
- Master's degree in Science, Engineering, or related field
- PhD in Science, Engineering, or related field
Salary/Compensations
- $129,600.00 - $179,600.00
Benefits
- Competitive annual discretionary bonus program
- Opportunity for annual RSU grants
- Highly competitive benefits package
About the Company
- Qualcomm Canada ULC is a leading technology innovator.
- Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
Equal Opportunity
- Qualcomm is an equal opportunity employer.
- If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process.
- You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here.
- Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.
- Qualcomm is also committed to making our workplace accessible for individuals with disabilities.