Impress employers and recruiters.
Choose from hundreds of resume examples.

Impress employers and recruiters.
Choose from hundreds of resume examples.
Tailor your resume to this Design Verification Architect / Director role.
Rezi rewrites your resume against Cadence Design Systems's job description. Free.

Tailor your resume to this Design Verification Architect / Director role.
Rezi rewrites your resume against Cadence Design Systems's job description. Free.
Don't guess if your resume is good enough.
See how it scores against the Design Verification Architect / Director posting at Cadence Design Systems — free, in seconds.

Don't guess if your resume is good enough.
See how it scores against the Design Verification Architect / Director posting at Cadence Design Systems — free, in seconds.
About the Role
Lead and manage the Processor Verification team, responsible for the verification of microprocessor cores and their peripherals. Relevant experience in-order/out-of-order CPU cores and memory subsystem strongly preferred.
Responsibilities
- Crafting verification plans and executing them to verify highly complex CPU designs.
- Implement simulation or emulation testbenches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals.
- Responsible for coverage collection and closure.
- Work closely with cross-functional teams (DV/Arch/Design/FW) to identify coverage scope.
- Track and report the work of 7-10 engineers.
Requirements
- 17+ years of design verification experience
- Proven experience at leading/managing team.
- Strong managerial, leadership and interpersonal skills
- Excellent knowledge of computer architecture and design verification fundamentals
- Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches
- Exposure to scripting languages like Perl, Unix shell or similar languages
- Experience with assembly language programming required
- Experience with Formal Verification will be a plus
- Experience with the development of fully automated flows
- Experience with Gate Level Simulations
- Excellent written and oral communication skills necessary
- Knowledge of processor verification required
Skills
- System Verilog
- UVM
- Perl
- Unix shell
- Assembly language programming
Location
- San Jose, CA
- Austin, TX
Work Type
- Full-time
Experience Level
- 17+ years of design verification experience
Education Level
- BS (or higher) in EE/Computer Engineering
Salary/Compensations
- $185,500 to $344,500
Benefits
- Incentive compensation: bonus, equity
- Competitive On Target Earnings (OTE) incentive compensation structure for sales positions
- Paid vacation and paid holidays
- 401(k) plan with employer match
- Employee stock purchase plan
- Variety of medical, dental and vision plan options
About the Company
- At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- We’re doing work that matters. Help us solve what others can’t.