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About the Role
EP (Embedded Processing Product Group) is expanding its product portfolio to include RL78, RX, RA, and RZ for smart appliances, energy measurement, building automation, and in-vehicle endpoint devices, aiming for a 8-12% CAGR from 2026 onwards. To support this growth, we are seeking an experienced physical design engineer to lead backend development, enhance quality, performance, and cost competitiveness. You will join a global team across Japan, China, Germany, Vietnam, and India, utilizing cutting-edge EDA and AI design technologies for next-generation semiconductor products.
Responsibilities
- Layout design (PnR) tasks (ICC2 / FusionCompiler-BE / Innovus), including floor planning, hierarchical design, power design, and analog routing.
- Layout verification (PV) tasks (Calibre / Pegasus / Voltus).
Requirements
- Knowledge and experience in layout design and verification tasks.
Skills
- Experience using EDA tools for LSI layout design and verification (Cadence, Synopsys, Siemens, etc.).
Location
- Japan
Work Type
- Full-time
- Onsite
Experience Level
- Experienced
Benefits
- Competitive compensation package.
- Comprehensive benefits package.
About the Company
- Renesas is a global leader in embedded semiconductor solutions, driven by the purpose 'To Make Our Lives Easier'. With over 21,000 engineers and problem solvers in 30+ countries, we contribute to world-leading technology development in automotive, industrial, infrastructure, and IoT sectors, aiming for a safer, healthier, greener, and smarter future.
- Our corporate culture, 'TAGIE' (Transparent, Agile, Global, Innovative, Entrepreneurial), is the core of how we work, grow, and pursue our purpose. This collaborative spirit and challenging mindset enable us to transform industries through semiconductor technology and contribute to people's lives worldwide.