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About the Role
We are looking for a SoC Design Verification Engineer to support the complete verification of our innovative System-on-Chip (SoC). This critical role encompasses our RISC-V core, network, and 3rd-party peripheral IP integrations. You will be responsible for developing comprehensive verification plans, building testbenches, and ensuring the highest level of design quality and functional correctness before tape-out.
Responsibilities
- Develop and execute verification plans for complex SoC digital designs.
- Create and maintain UVM/SystemVerilog based testbenches and environments.
- Write, debug, and execute constrained-random and directed test cases.
- Implement RISC-V ISA compliance tests.
- Perform functional coverage analysis and close coverage gaps.
- Perform regression runs, analyze failures, and drive bug closure.
- Connect simulations to real user interfaces, stimulus generators, and checkers.
- Collaborate closely with RTL design engineers, architects, and software teams.
- Contribute to the development and improvement of verification methodologies and automation scripts.
- Perform preliminary debug of discovered issues.
Requirements
- A Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering (or related field).
- 3+ years of hands-on experience in ASIC/SoC design verification.
- Strong proficiency in SystemVerilog, UVM, and simulation tools (e.g., Xcelium).
- Solid understanding of digital design fundamentals, RTL design, and synthesis flow.
- Experience with functional coverage, assertions, and scoreboarding.
- Strong scripting and programming skills (Python, Perl, TCL, C/C++).
- Knowledge of common bus protocols (AXI, AHB, PCIe, DDR4/5, etc.).
- Working knowledge of version control and continuous integration tools (e.g., Git, Jenkins, Jira, and Confluence).
- Solid debugging skills, analytical thinking, and attention to detail.
- Experience with Formal verification (Conformal LEC).
- Hands-on experience with emulation systems (Zebu, Palladium) or FPGA prototypes.
- Experience with Cadence EDA tools.
Skills
- SystemVerilog
- UVM
- Xcelium
- Python
- Perl
- TCL
- C/C++
- AXI
- AHB
- PCIe
- DDR4/5
- Git
- Jenkins
- Jira
- Confluence
- Formal verification
- Conformal LEC
- Emulation systems
- Zebu
- Palladium
- FPGA prototypes
- Cadence EDA tools
Location
- Austin
- Remote
Work Type
- Hybrid
- Remote
- Full-time
Experience Level
- 3+ years
Education Level
- Bachelor's degree
- Master's degree
Benefits
- Competitive salaries
- Benefits
- Equity
About the Company
- InspireSemi is revolutionizing high-performance computing with a groundbreaking architecture packing thousands of 64-bit CPU cores onto a single chip, tightly integrated with a high-performance interconnect.
- Our mission is to make high-performance computing more accessible and energy-efficient, with a developer-friendly programming model.