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About the Role
We are seeking power integrity engineers to ensure stable power delivery across all levels, from rack/tray to die and core.
Responsibilities
- Perform PDN analysis and design for large die, high TDP chips.
- Conduct PDN analysis and design for advanced node (7nm and lower) chips.
- Collaborate with package architects on passive design within constraints.
- Work with ASIC and microarchitecture teams to meet power integrity goals under manufacturing constraints.
Requirements
- Experience with large die, high TDP chip PDN analysis and design.
- Experience with advanced node (7nm and lower) chip PDN analysis and design.
- Ability to work with package architects to determine best passives design within a given set of constraints.
- Ability to work with ASIC and microarchitecture team to hit power integrity goals given manufacturing design constraints.
Skills
- Power integrity analysis
- Power delivery network (PDN) design
- Passive design
- ASIC design
- Microarchitecture
- WSI (wafer-scale integration) systems
- Board and system-level power delivery network analysis and design
- Low voltage die power delivery network analysis and design
- Many voltage domain power delivery network design and analysis
- IVR based design