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About the Role
We are seeking an XPU Architect to lead the XPU compute engine architecture for our A-0 and A-1 systems. This role will involve creative utilization of existing third-party IP to address bandwidth and memory system interface challenges, with future generations focusing on semi-custom and custom designs.
Responsibilities
- Own the XPU compute engine architecture of the A-0 and A-1 systems.
- Leverage existing 3rd party IP creatively to solve bandwidth and memory system interface challenges.
- Contribute to future generations of semi-custom and custom XPU designs.
Requirements
- Previous experience architecting and owning a high performance, high TDP ASIC (e.g., AI chips, network switch chips, high performance CPUs, or similar).
- Knowledge of computer architecture and silicon implementation, including realistic constraints.
- Deep understanding of AI workloads, especially low latency LLM inference.
- Understanding of workload and system level bottlenecks, particularly around inference, including interconnect, memory capacity, bandwidth, and latency.
- Hands-on experience with AI chip architecture and tapeouts.
- End-to-end ownership of at least one AI ASIC project.
- History of product delivery.
- Experience with HBM-based AI chip architecture.
- Experience proposing novel chip architectures.
Skills
- XPU architecture
- ASIC architecture
- High performance computing
- High TDP design
- Computer architecture
- Silicon implementation
- AI workloads
- LLM inference
- System bottlenecks
- Interconnect
- Memory bandwidth
- Memory latency
- HBM
- Chip architecture innovation