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About the Role
Own the logical architecture for the A-0 and A-1 wafer products, working with chip architects to synthesize the final wafer-level architecture.
Requirements
- Deep understanding and hands-on experience in the design process of AI chips, such as GPUs, TPUs, XPUs, custom ASICs, etc.
- Understanding of memory sub-systems and interactions in multi-die systems.
- Understanding of LLM inference workloads, especially at a software level and its implications for hardware (system, package, network, die-level) systems.
- Experience with multi-die designs.
- Experience with MCM and chiplet based architectures and architectural partitioning across them.
- Experience in partitioning workloads across multiple chips and chip packages.
Skills
- AI chip design
- Memory sub-systems
- LLM inference workloads
- Multi-die designs
- MCM architectures
- Chiplet based architectures
- Workload partitioning