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About the Role
We are seeking exceptional design verification engineers to ensure our high-performance custom silicon is functionally correct. You will define test bench boundaries and implement test environments across a variety of verification methodologies, collaborating with RTL design, performance modeling and verification, and compiler teams.
Responsibilities
- Define comprehensive verification plans by extracting features from architectural and micro-architectural specifications for complex blocks.
- Architect and implement scalable, reusable, and robust test benches using SystemVerilog and UVM.
- Develop complex sequences and test cases to achieve high functional coverage, ensuring the design handles architectural corner cases and error conditions.
- Define and implement functional coverage models and perform detailed code coverage analysis to quantify verification progress.
- Leverage formal methods (SVA, Property Checking) where applicable to exhaustively prove the correctness of critical logic.
- Use emulation and prototyping platforms like ZeBu/HAPS and Palladium/Protium to perform scaled testing.
- Debug failures using waveform viewers and work closely with RTL designers to resolve functional bugs and architectural non-compliance.
- Build and maintain regression flows and productivity tools using Python, Perl, Bash, or TCL to streamline the verification cycle.
Requirements
- Bachelor’s degree in Electrical Engineering or Computer Engineering or Computer Science, and 5+ years industry experience.
- Deep, hands-on experience building UVM-based environments (Agents, Scoreboards, Drivers, Monitors, and Predictors).
- Expert command of SystemVerilog for verification, including OOP principles, randomization, and functional coverage.
- Strong understanding of computer architecture, including pipelines, cache coherency protocols, memory consistency models, and high-speed interconnects (e.g., AXI, CHI).
- Proven track record of verifying high-performance silicon (CPU, GPU, AI accelerator, or complex SoC).
- A highly collaborative mindset and a bias for action to push boundaries and co-design effectively with other engineers.
- Proficiency SystemVerilog Assertions (SVA) and formal tools (Jasper, VC Formal) to catch temporal logic bugs at the source.
- Understanding of emulation and prototyping solutions and test environments.
- Hands-on experience in post-Silicon bringup, testing, and debug.
- Experience in workflow management, CI/CD, regression definition and visibility, EDA tool configuration and usage, and other infrastructure tasks.
Skills
- SystemVerilog
- UVM
- Constrained-Random Testing
- Functional Coverage
- Formal Verification
- Emulation
- Python
- Perl
- Bash
- TCL
- SystemVerilog Assertions (SVA)
- Computer Architecture
- Pipelines
- Cache Coherency Protocols
- Memory Consistency Models
- High-Speed Interconnects (AXI, CHI)
- Post-Silicon Bringup
- Workflow Management
- CI/CD
- EDA Tool Configuration
Location
- Austin, Texas
- Palo Alto, California
Work Type
- Onsite
Experience Level
- 5+ years industry experience
Education Level
- Bachelor’s degree in Electrical Engineering or Computer Engineering or Computer Science
Salary/Compensations
- $200,000 - $420,000 USD
Benefits
- Generous health, dental, and vision benefits
- Unlimited PTO
- Relocation support
- Visa Sponsorship
About the Company
- At River AI, our mission is to create personal AI owned and shaped by each individual.
- We are rewriting the entire stack from scratch: personal hardware for local inference, bespoke training infrastructure, next-generation UIs, and frontier deep learning research.
- We are scientists, engineers, and builders from the industry's top tech companies and AI labs.
- We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre-training infrastructure behind today's frontier models.