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About the Role
We are seeking exceptional hardware performance engineers to architect, model, and correlate high-performance custom silicon. You will develop high-fidelity simulators to predict how our AI accelerator architecture and SoC system will handle real-world AI models. You will take ownership of performance models, ISA and kernel optimization, and FPGA emulators for software development. You will be collaborating both up and down the stack with compiler, IR, and software teams, as well as with RTL design engineers.
Responsibilities
- Design and implement high-performance and functional models of complex hardware using C++ and/or SystemC.
- Conduct "what-if" studies to evaluate architectural changes and their impact on IPC, MFU, TTFT, and total execution time.
- Analyze and profile AI kernels and software stacks to generate representative traces that stress-test the hardware models.
- Collaborate with compiler and kernel teams to optimize software mapping to hardware, ensuring the architecture supports emerging algorithmic breakthroughs efficiently.
- Validate the performance model against RTL and pre-silicon emulators to ensure the model’s accuracy remains within strict tolerance levels.
- Identify and quantify system-level bottlenecks, ranging from instruction-level parallelism (ILP) limits to bandwidth throttling to utilization.
Requirements
- Bachelor’s degree in Electrical Engineering or Computer Engineering or Computer Science, and 5+ years practical industry experience working with advanced process nodes (7nm or below).
- Expert proficiency in C/C++ or event-driven simulation environments like SystemC
- Hands-on experience with how compilers transform code (LLVM/GCC/XLA) and how high-performance kernels (CUDA/Triton) interact with the underlying ISA.
- Expert knowledge in Computer Architecture of at least one style of chip, including SoCs, CPUs, GPUs, or AI accelerators
- Experience with profiling hardware with performance counters, hardware profilers, and trace analysis tools to dissect application behavior.
- A highly collaborative mindset to push boundaries and co-design effectively with other engineers.
- Hands-on experience in pre-silicon RTL/emulator and/or post-silicon performance validation
- Knowledge or experience of QEMU models for pre-silicon software development
- Proficiency in scripting for data post-processing, visualization of simulation results, and automation of massive regression suites.
Skills
- C++
- SystemC
- LLVM
- GCC
- XLA
- CUDA
- Triton
- SoCs
- CPUs
- GPUs
- AI accelerators
- Performance counters
- Hardware profilers
- Trace analysis tools
- QEMU models
- Scripting
Location
- Austin, Texas
- Palo Alto, California
Work Type
- Onsite
Experience Level
- 5+ years practical industry experience
Education Level
- Bachelor’s degree in Electrical Engineering or Computer Engineering or Computer Science
Salary/Compensations
- $200,000 - $420,000 USD
Benefits
- Generous health, dental, and vision benefits
- Unlimited PTO
- Relocation support
- Visa sponsorship
About the Company
- At River AI, our mission is to create personal AI owned and shaped by each individual.
- We are rewriting the entire stack from scratch: personal hardware for local inference, custom training infrastructure, next-generation UIs, and frontier deep learning research.
- We are scientists, engineers, and builders from the industry's top tech companies and AI labs.
- We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre-training infrastructure behind today's frontier models.