Impress employers and recruiters.
Choose from hundreds of resume examples.
Impress employers and recruiters.
Choose from hundreds of resume examples.
Tailor your resume to this Senior Design Verification Engineer role.
Rezi rewrites your resume against Astera Labs's job description. Free.
Tailor your resume to this Senior Design Verification Engineer role.
Rezi rewrites your resume against Astera Labs's job description. Free.
Don't guess if your resume is good enough.
See how it scores against the Senior Design Verification Engineer posting at Astera Labs — free, in seconds.
Don't guess if your resume is good enough.
See how it scores against the Senior Design Verification Engineer posting at Astera Labs — free, in seconds.
About the Role
As a Senior Design Verification Engineer, you will build and validate complex connectivity silicon for next-generation AI infrastructure. You will develop scalable verification environments, integrate UVM and C/C++ workflows, and collaborate with RTL designers to resolve issues across simulation, co-simulation, and emulation. This role offers a chance to contribute to the verification lifecycle at a hyper-growth connectivity company, delivering reliable, high-bandwidth products for rack-scale AI systems.
Responsibilities
- Build and maintain UVM-based verification environments using SystemVerilog and C/C++ integration through DPI/PLI.
- Translate design specifications into verification plans, test strategies, and reusable test sequences.
- Develop VIP abstraction layers that simplify and scale verification across projects and platforms.
- Create directed and constrained-random tests, transaction-level sequences, and user-controlled random constraints.
- Write assertions and cover properties, analyze coverage data, and drive closure against verification goals.
- Automate verification infrastructure and regression workflows using Python or Perl.
- Collaborate with RTL designers and other engineers to isolate, debug, and resolve failures across simulation, co-simulation, and FPGA-based emulation.
- Apply third-party verification IP to validate protocols including PCIe, Ethernet, InfiniBand, DDR, NVMe, and USB.
- Contribute to technical reviews, communicate verification status clearly, and manage priorities across multiple deliverables.
Requirements
- Bachelor’s degree in Electrical Engineering or a related field.
- 2 - 5 years of experience developing or verifying complex SoC or silicon products.
- Hands-on experience with SystemVerilog, UVM, and C/C++ in production verification environments.
- Experience integrating C/C++ with SystemVerilog environments using DPI or PLI.
- Experience developing verification infrastructure and tests in directed and constrained-random environments.
- Strong debugging, prioritization, collaboration, and communication skills.
- Authorized to work in Canada.
Skills
- SystemVerilog
- UVM
- C/C++
- DPI/PLI
- Python
- Perl
- PCIe
- Ethernet
- InfiniBand
- DDR
- NVMe
- USB
- FPGA-based verification
- FPGA-based emulation
- SoC software debugging
- kernels
- device drivers
- U-Boot
- verification IP
- protocol-level modeling
Location
- Canada
Work Type
- Full-time
Experience Level
- Senior
- 2 - 5 years
Education Level
- Bachelor’s degree
About the Company
- Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions.
- By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI.
- Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
- The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.
Equal Opportunity
- We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.