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About the Role

As a Ph.D. Intern in Advanced Packaging & Physical Integration, you will work on packaging design and analysis challenges directly related to production AI accelerator and connectivity platforms. This role offers the unique opportunity to solve packaging problems that are integrated into the world's most advanced AI silicon, gaining experience that cannot be replicated in a university lab.

Responsibilities

Perform signal integrity (SI) and power integrity (PI) analysis for high-speed interfaces, including 224G SerDes, die-to-die interconnects, and HBM interfaces, across multi-die package substrates and interposers.
Develop and execute thermal and mechanical simulation models for advanced 2.5D and 3D chiplet packages, evaluating heat dissipation, warpage, and reliability under production conditions.
Contribute to the physical design and layout of package substrates, RDL interposers, and chiplet integration schemes for custom AI accelerator platforms.
Collaborate with chip design, assembly, and test engineering teams to validate packaging assumptions against silicon measurements and production data.
Use industry-standard EDA and simulation tools, such as Ansys, Cadence Sigrity, or equivalent, to model and optimize package-level electrical, thermal, and mechanical performance.
Present analysis results and design recommendations to the engineering team and contribute to packaging design reviews.

Requirements

Currently enrolled in a Ph.D. program in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field, with a research focus in advanced packaging, signal/power integrity, thermal engineering, or heterogeneous integration.
Demonstrate research or project experience in one or more of the following: package-level SI/PI analysis, thermal-mechanical simulation, 2.5D/3D chiplet integration, substrate or interposer design, or high-speed interconnect characterization.
Apply strong fundamentals in electromagnetics, heat transfer, or materials mechanics to build and interpret simulation models that inform real packaging design decisions.
Use simulation tools relevant to your research area (Ansys HFSS, Ansys Icepak, Cadence Sigrity, or equivalent) with confidence and independence.
Communicate analysis results and design tradeoffs clearly, presenting work to the engineering team and defending recommendations.
Experience with high-speed serial interface SI analysis, including eye diagram analysis, impedance matching, crosstalk, and return loss, at 100G/lane speeds or above.
Familiarity with advanced packaging technologies including CoWoS, FOPLP, RDL interposers, or flip-chip BGA.
Exposure to co-packaged optics (CPO) integration, optical engine assembly, or photonic-electronic co-design.
Experience with power delivery network (PDN) design and analysis for high-current, high-frequency applications.
Familiarity with design-for-manufacturing (DFM) and reliability considerations for chiplet-based multi-die packages.
Must be eligible to access technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). Applicants may be subject to an export license review process.

Skills

Signal Integrity (SI)
Power Integrity (PI)
224G SerDes analysis
Die-to-die interconnect analysis
HBM interface analysis
Thermal simulation
Mechanical simulation
2.5D/3D chiplet package simulation
Physical design
Layout design
Package substrate design
RDL interposer design
Chiplet integration
EDA tools
Ansys
Cadence Sigrity
Electromagnetics
Heat transfer
Materials mechanics
Eye diagram analysis
Impedance matching
Crosstalk analysis
Return loss analysis
CoWoS
FOPLP
Flip-chip BGA
Co-packaged optics (CPO) integration
Optical engine assembly
Photonic-electronic co-design
Power delivery network (PDN) design
Design-for-manufacturing (DFM)
Reliability considerations

Location

Remote

Work Type

Internship
Full-time

Experience Level

Ph.D. Candidate

Education Level

Ph.D.

Salary/Compensations

$37 - $73 per hour

Benefits

Medical coverage
Dental coverage
Vision coverage
Perks and discounts
Robust mental health resources
Paid holidays

About the Company

Marvell's semiconductor solutions are essential building blocks for the data infrastructure connecting the world, enabling new possibilities across enterprise, cloud, AI, and carrier architectures.
The company focuses on purposeful and enduring innovation, providing a platform to thrive, learn, and lead.
The advanced packaging team integrates compute silicon, high-bandwidth memory, optical I/O, and die-to-die interconnects into unified systems for custom XPUs, AI accelerators, and high-speed connectivity platforms used by hyperscalers.
Marvell's packaging work is production-qualified and shipping at hyperscale, featuring an industry-first modular RDL interposer platform and integration of Co-Packaged Optics.

Equal Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.