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About the Role

Marvell's Ph.D. Intern Program places doctoral candidates directly inside active architecture and research efforts. Projects are selected because they sit at the intersection of Marvell's most pressing systems-level challenges and the computer architecture, signal processing theory, and networking algorithms that define doctoral research in electrical engineering and computer science. The work is the applied dimension of the academic research a Ph.D. candidate is already pursuing — conducted at production scale, against real system constraints, for hyperscale customers building the world's most advanced AI infrastructure. What you will take away is something no simulation or academic dataset can replicate: the experience of seeing your architectural decisions and algorithms deployed in silicon running inside the world's largest AI data centers.

Responsibilities

Architect, model, and evaluate system-level designs for switching, interconnect, or DSP applications — developing analytical models and simulations that inform real silicon architecture decisions
Develop and optimize DSP algorithms for high-speed electrical or optical links, including equalization, FEC, timing recovery, and signal integrity techniques for PAM4, coherent, or emerging modulation formats
Design and analyze network architectures for AI fabrics — including forwarding pipeline design, congestion control, traffic management, and load balancing for scale-up, scale-out, and scale-across applications
Collaborate with analog, digital, and software engineering teams to validate architectural assumptions against real hardware and silicon measurements
Build behavioral models and simulations in MATLAB, Python, or C++ to evaluate performance tradeoffs across architecture, power, latency, and bandwidth
Present architectural proposals and algorithm results to engineering leadership and contribute to internal technical documentation and design reviews

Requirements

Currently enrolled in a Ph.D. program in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with a research focus in computer architecture, digital signal processing, communications systems, or networking
Demonstrate research experience in one or more of the following: processor or switch architecture, DSP algorithm design for high-speed communications, network protocol design, or system-level modeling and simulation
Apply strong analytical fundamentals — whether in signal processing theory, queuing theory, information theory, or computer architecture — to real engineering problems with measurable performance targets
Model and simulate complex systems using tools such as MATLAB, Python, or C/C++; familiarity with hardware description languages (Verilog, SystemVerilog) or cycle-accurate simulation is a plus
Communicate architectural decisions and algorithm tradeoffs clearly — you will present your work to engineering teams and defend your approach against real system constraints
Familiarity with Ethernet switching architectures, programmable forwarding pipelines, or network congestion control algorithms for large-scale AI fabrics
Experience with PAM4, coherent, or high-speed serial link DSP — including equalization, FEC, or timing and synchronization algorithms
Exposure to custom compute architecture, SoC design, or XPU/GPU interconnect systems
Knowledge of Ultra Ethernet Consortium (UEC) protocols, RoCE, or RDMA networking for AI workloads
Experience with open networking platforms such as SONiC or P4-based programmable pipelines
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

Skills

Computer architecture
DSP algorithm design
Communications systems
Networking
Signal processing theory
Queuing theory
Information theory
MATLAB
Python
C++
Verilog
SystemVerilog
Ethernet switching architectures
Programmable forwarding pipelines
Network congestion control algorithms
PAM4
Coherent DSP
High-speed serial link DSP
Equalization
FEC
Timing and synchronization algorithms
Custom compute architecture
SoC design
XPU/GPU interconnect systems
Ultra Ethernet Consortium (UEC) protocols
RoCE
RDMA networking
SONiC
P4-based programmable pipelines

Experience Level

Ph.D. Intern

Education Level

Ph.D.

Salary/Compensations

$31 - $62 per hour

Benefits

Medical coverage
Dental coverage
Vision coverage
Perks and discounts
Robust mental health resources
Paid holidays

About the Company

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Equal Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.