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About the Role
We are looking for a Design Verification Engineer to join our global development team. This role is crucial for ensuring the quality and reliability of our next-generation physical AI SoCs by leading functional verification from IP to SoC levels. You will be responsible for developing verification strategies, building environments, and driving coverage closure.
Responsibilities
- Perform functional verification for SoCs targeting industrial equipment and physical AI.
- Verify subsystems including Arm® CPU subsystems and AMBA Bus architectures.
- Verify image input systems, including Camera Interfaces (e.g., MIPI CSI-2).
- Verify image processing subsystems utilizing Graphics, Vision AI, and AI accelerators.
- Create Verification Plans and define verification items.
- Build verification environments.
- Drive Coverage Closure using Functional Coverage and Code Coverage.
- Collaborate with RTL design, physical design, and software teams.
Requirements
- Experience with functional verification using SystemVerilog and UVM (or Specman).
- Experience in functional verification of digital circuits, SoCs, or IPs.
- Experience with simulation-based debugging and defect analysis.
- Experience in creating Verification Plans and verification scenarios.
- Ability to communicate smoothly in English with global development teams and drive development through collaboration with related departments.
- Over 3 years of practical experience in digital functional verification using SystemVerilog/UVM.
Skills
- SystemVerilog
- UVM
- Specman
- Digital circuit verification
- SoC verification
- IP verification
- Simulation-based debugging
- Defect analysis
- Verification Plan creation
- Verification scenario creation
- English communication
- Arm® CPU subsystem verification
- AMBA AXI/AHB/APB bus architecture knowledge
- Camera Interface (MIPI CSI-2) verification
- Graphics IP verification
- GPU verification
- Vision AI verification
- Image recognition verification
- AI accelerator verification
- Functional Coverage
- Coverage Closure
- Regression management
- Formal Verification (FV)
- Cadence JasperGold
- Synopsys VC Formal
Location
- Remote Work Available: No
Work Type
- Regular (PERM)
Experience Level
- 3 years of practical experience in digital functional verification using SystemVerilog/UVM
Benefits
- Competitive compensation package
- Comprehensive benefits package
About the Company
- Renesas is a global company providing embedded semiconductor solutions, aiming to 'Make Our Lives Easier'.
- With over 21,000 engineers and problem solvers in more than 30 countries, we contribute to the development of world-leading technologies in automotive, industrial, infrastructure, and IoT fields.
- We contribute to realizing a safer, healthier, more environmentally friendly, and smarter future through semiconductor technology.
- Our core corporate culture is 'TAGIE' (Transparent, Agile, Global, Innovative, Entrepreneurial), which guides our work, growth, and pursuit of our Purpose.
- This collaborative spirit and challenging mindset enable us to transform industries and improve lives worldwide through semiconductor technology.